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Hao Zhang 0145

dblp:55/2270-145 · DBLP profile ↗
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3ranked-venue papers
2as first author
3since 2021 · last 2026
0000-0002-9745-4767ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 44% Memory systems · 28% Reconfigurable computing and FPGAs · 22%
Software engineering, system software, and programming languages
1 paper
Program synthesis and code generation · 44% Software maintenance and evolution · 44% Empirical software engineering · 13%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software maintenance and evolution › software documentation
commit message generation
1.012026
An Empirical Study of Parameter-Efficient Fine-Tuning in Code Change Learning and Beyond · IEEE Trans. Software Eng. 2026
Program synthesis and code generation
parameter-efficient fine-tuning
1.012026
An Empirical Study of Parameter-Efficient Fine-Tuning in Code Change Learning and Beyond · IEEE Trans. Software Eng. 2026
Memory systems › processing-in-memory
computing-in-memory
0.812024
Implementing Neural Networks on Nonvolatile FPGAs With Reprogramming · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator
DNN accelerator
0.812024
Implementing Neural Networks on Nonvolatile FPGAs With Reprogramming · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network inference
0.812024
Implementing Neural Networks on Nonvolatile FPGAs With Reprogramming · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Reconfigurable computing and FPGAs › FPGA architecture
nonvolatile FPGA
0.812024
Implementing Neural Networks on Nonvolatile FPGAs With Reprogramming · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Empirical software engineering › mining software repositories › defect prediction
just-in-time defect prediction
0.312026
An Empirical Study of Parameter-Efficient Fine-Tuning in Code Change Learning and Beyond · IEEE Trans. Software Eng. 2026
Memory systems
non-volatile memory
0.212024
Implementing Neural Networks on Nonvolatile FPGAs With Reprogramming · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Cloud and datacenter computing › application deployment
task deployment
0.212024
Implementing Neural Networks on Nonvolatile FPGAs With Reprogramming · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024

Methods — techniques the papers use, named apart from their topics

probing · 1.0pret · 1.0full-model fine-tuning · 1.0PT · 1.0LoRA · 1.0AT · 1.0task switching · 0.8task deployment optimization · 0.8
YearPublicationVenuePosition
2026 An Empirical Study of Parameter-Efficient Fine-Tuning in Code Change Learning and Beyond
abstract
Compared to Full-Model Fine-Tuning (FMFT), Parameter-Efficient Fine-Tuning (PEFT) has demonstrated superior efficacy and efficiency in several code understanding tasks, owing to PEFT’s ability to alleviate the catastrophic forgetting issue of Pre-trained Language Models (PLMs) by updating only a small number of parameters. However, existing studies primarily involve static code comprehension, aligning with the pre-training paradigm of recent PLMs and facilitating knowledge transfer, but they do not account for dynamic code changes. Thus, it remains unclear whether PEFT outperforms FMFT in task-specific adaptation for code-change-related tasks.To address this question, we examine four prevalent PEFT methods (i.e., AT, LoRA, PT, and PreT) and compare their performance with FMFT across seven popular PLMs. In experiments, two widely studied code-change-related tasks, i.e., Just-In-Time Defect Prediction (JIT-DP) and Commit Message Generation (CMG) are involved, demonstrating that the four PEFT methods can surpass FMFT on JIT-DP but only exhibit comparable performances at best on CMG in common scenarios. While in cross-lingual and low-resource scenarios, they exhibit relative superiority. Afterward, a series of probing tasks from both static and dynamic perspectives are conducted in this paper, offering detailed explanations for the efficacy of PEFT and FMFT. Inspired by the distinctive advantages of PEFT and FMFT in their layer-wise probing results, we propose Pasta$k$, a self-adaPtive efficient layer-specific tuning framework for PLMs in code change learning, which combines FMFT and PEFT during the domain adaptation according to the guidance of probing results. Experiments in the CMG task demonstrate that Pasta$k$surpasses diverse PEFT methods in effectiveness. Even, Pasta$k$outperforms FMFT by 1.48%, 3.21%, and 1.87% at most in terms of BLEU, Meteor, and Rouge-L, while saving 26.26% and 20.65% in terms of training time and computational memory compared with FMFT.
Shuo Liu 0020, Jacky W. Keung, Zhi Jin 0001, Zhen Yang 0022, Fang Liu 0032, Hao Zhang 0145
IEEE Trans. Software Eng.6
2024 Implementing Neural Networks on Nonvolatile FPGAs With Reprogramming
abstract
NV-FPGAs have attracted significant attention in research due to their high density, low leakage power, and reduced error rates. The nonvolatile memory (NVM) crossbar’s compute-in-memory (CiM) capability further enables NV-FPGAs to execute high-efficiency, high-throughput neural network (NN) inference tasks. However, with the rapid increase in network size and considering that the parameter size often exceeds the memory capacity of the field programmable gate array (FPGA), implementing the entire network on a single FPGA chip becomes impractical. In this article, we utilize FPGA’s inherent run time reprogramming feature to implement oversized NNs on NV-FPGAs. This approach splits NN models into multiple tasks for the cyclical execution. Specifically, we propose a performance-driven task adapter (PD-Adapter), which aims to achieve high-performance NN inference by employing the task deployment to optimize settings, such as processing element size and quantity, and the task switching to select the most suitable switching type for each task. We integrate the proposed PD-Adapter into an open-source toolchain and evaluate it. Experimental results demonstrate that the PD-Adapter can achieve a run time reduction of 85.37% and 76.12% compared to the baseline and execution-time-first policy, respectively.
Hao Zhang 0145, Jian Zuo, Huichuan Zheng, Meihan Luo, Mengying Zhao
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2022 Lifetime improvement through adaptive reconfiguration for nonvolatile FPGAs
Hao Zhang 0145, Huichuan Zheng, Shuangliang Li, Mengying Zhao, Xiaojun Cai
J. Syst. Archit.1