This paper addresses post-routing capacitance extraction duringperformance-driven layout. We first show how basic driversin process technology (planarization and minimum metal densityrequirements) actually simplify the extraction problem; wedo this by proposing and validating five "foundations" throughdetailed experiments with representative 0.18μm process parametersand a 3-D field solver.We then present a simple yetaccurate 2 1/2-D extraction methodology directly based on thefoundations.This methodology has been productized and isbeing shipped with the Cadence Silicon Ensemble 5.0 product.We conclude that the 2 1/2-D approach has sufficient accuracyfor current and near-term process generations.

We have developed a gate matrix layout synthesis tool which utilizes folding technique on both rows and columns. The conventional interval graph model and the recently proposed dynamic net-list representation can not fully depict circuit schematics such as inter-net connections. The incomplete representations may mislead the search process for an optimal solution during the layout partitioning and the gate ordering phases. We propose a new graph-based model called hierarchical dynamic net-list to improve the schematic representation. Based on the new model, the folded layout area in the partitioning phase can be more accurately estimated. The new gate ordering algorithm proposed by us also takes the advantages of the hierarchical dynamic net-list model to handle the gate placement in the folded layouts. The experimental results show 12% to 15% improvement in layout area for small circuits and 30% improvement for a large circuit.