Deflection routing resolves output port contention in packet switched multiprocessor interconnection networks by granting the preferred port to the highest priority packet and directing contending packets out other ports. When combined with optical links and switches, deflection routing yields simple bufferless nodes, high bit rates, scalable throughput, and low latency. We discuss the problem of packet synchronization in synchronous optical deflection networks with nodes distributed across boards, racks, and cabinets. Synchronous operation is feasible due to very predictable optical propagation delays. A routing control processor at each node examines arriving packets and assigns them to output ports. Packets arriving on different input ports must be bit wise aligned; there are no elastic buffers to correct for mismatched arrivals. "Time of flight" packet synchronization is done by balancing link delays during network design. Using a directed graph network model, we formulate a constrained minimization problem for minimizing link delays subject to synchronization and packaging constraints. We demonstrate our method on a ShuffleNet graph, and show modifications to handle multiple packet sizes and latency critical paths.

We describe the design and implementation of a packet-switched fiber optic interconnect prototype with a ShuffleNet topology, intended for use in shared-memory multiprocessors. Coupled with existing latency-hiding mechanisms, it can reduce latency to remote memory locations. Nodes use deflection routing to resolve contention. Each node contains a processor, memory, photonic switch, and packet routing processor. Payload remains in optical form from source to final destination. Each host processor is a commercial workstation with FIFO interfaces between its bus and the photonic switch. A global clock is distributed optically to each node to minimize skew. Component costs and network performance figures are presented for various node configurations including bit-per-wavelength and fiber-parallel packet formats. Our efforts to implement and test a practical interconnect including real host computers distinguishes our work from previous theoretical and experimental work. We summarize obstacles we encountered and discuss future work.