A systematic approach to test analog array-processor neural chips is presented. Unique testing problems for analog neural chips are described and effective solutions are discussed. Based on the hierarchical methodology, testing of analog array-processor neural chips can be systematically addressed. The test results for programmable analog neural chips fabricated by a 2- mu m CMOS process are presented. These chips contain 25 neurons and 1600 synapses.>

A novel approach to the design of digital and analog VLSI with built-in reliability is presented. Physics-based reliability models for key failure mechanisms in VLSI circuits are used to achieve accurate and efficient circuit-level reliability prediction and improvement. A prototype integrated-circuit reliability simulator (RELY) and experimental results on hot-carrier damage and metal electromigration effects are presented.>

The development of an MOS transistor charge and capacitance model for the analysis and design of VLSI circuits is described. The total stored charge in each of the gate, bulk, and channel regions is obtained by integrating the distributed charge densities over the thin-oxide area. Charge conservation is guaranteed in this model by using the terminal charges as the state variables. The capacitance expressions have the nonreciprocal property. Partition of channel charge into the drain and source components is 40/60 in the saturation region. In the triode region, this partition changes asymptotically to 50/50 as the gate voltage increases. The carrier-velocity saturation effect is incorporated through both the modification of channel quasi-Fermi level and the determination of drain saturation voltage. Implementation of the model in the SPICE circuit simulator has been achieved. Modeled results compare well with experimental data for transistors with channel lengths as small as 0.75 mu m.>