While the performance of smartphones becomes much higher, the application processor consumes considerable power. Thus, it is hard to meet thermal constraints by using conventional cooling techniques. Fortunately, since heat pipes can efficiently transfer the thermal energy from hot regions to cool regions, temperatures in hot regions can be reduced greatly. Hence, in the past three years, the heat pipe cooling techniques have been applied to smartphones by industries. However, although the time-consuming commercial simulation tools, such as ANSYS Fluent, can provide accurate thermal maps, they may lead to inefficiency during design stages. Besides, the compact thermal model for bended heat pipes is still underdeveloped. Therefore, efficient thermal simulation for smartphones with bended heat pipes should be developed for the design stage. Furthermore, the routing of bended heat pipe should be optimized to obtain more thermal energy transfer.

In advanced technologies, on-chip-variation (OCV) has accounted for a large proportion of clock skew, which limits the performance of a circuit. To mitigate the OCV problem, a mesh structure has been widely used in high-performance designs. Unfortunately, clock mesh structure also causes large power consumption and large power-ground surge current. Therefore, recently, several approaches have been proposed to apply resonant clock to reduce power consumption. However, previous works often suffer from area overhead because of the need to insert large decoupling capacitors. In this paper, we propose a novel resonant clock mesh structure, called ping-pong mesh, to overcome these drawbacks. Our ping-pong mesh contains two submeshes, each of which plays the role of the decoupling capacitor of the other, and the clocks in two submeshes operate in completely opposite phases. Our ping-pong mesh has the following two advantages: 1) a ping-pong mesh does not need additional decoupling capacitors as in previous works and 2) a ping-pong mesh can reduce the power-ground surge current about half of previous works. Benchmark data consistently show that our ping-pong mesh does work well in practice.

Runtime noise management systems typically rely on on-chip noise sensors to accurately capture voltage emergencies. As such, the threshold voltage for noise sensors to report emergencies serves as a critical tuning knob between the system failure rate and false alarms. Unfortunately, the problem of optimal threshold voltage computation remains open in literature despite its importance. The problem is further complicated by process variations, which introduce significant variations in load currents and thus in noise across different chips. A uniform noise margin may not work optimally for all the chips. In this paper, we first formulate the problem of minimizing the system alarm rate subject to a given system failure rate constraint. We then put forward a uniform scheme to find an optimal solution for all chips. Compared to a seemingly more intuitive approach which is too conservative, experimental results over a set of industrial designs show an average of 20.6% reduction in system alarm rate under the same system failure rate constraint. We further show that with the help of Iddqmeasurements during testing which reveal process variation information, it is possible and efficient to compute a per-chip optimal threshold voltage threshold. It further reduces the alarm rate by 12.3% on average compared with uniform threshold approach. To the best of the authors knowledge, this is the first in-depth study on optimal threshold voltage computation for noise sensors. We hope that it shall point out new directions for systematic studies of on-chip noise sensor utilization.

A sub-threshold design could provide a compelling approach to power critical applications. An exponential relationship exists, however, between the delay and the threshold voltage, that makes this design-time timing closure extremely difficult, if not impossible, to achieve. Several previous studies were focused on the technique of body biasing during post-silicon tuning for delay compensation. But they were mostly for super-threshold designs where spatially correlated ${L} _{\mathbf {eff}}$ variation dominates. They cannot be applied directly to sub-threshold designs in which purely random threshold voltage variations dominate. These works also assumed multiple body biasing voltage domains and multiple body biasing voltage levels, which involve significant design overhead. The problem of selective body biasing for post-silicon tuning of sub-threshold designs is examined in this paper. The possibility of using only one body bias voltage domain with a single body bias voltage is explored. The problem was formulated first as a linearly constrained statistical optimization model. The adaptive filtering concept from the signal processing community was then adopted so that an efficient, yet novel, solution could be developed. Using several 65 nm industrial designs, experimental results suggest that, compared with a seemingly more intuitive approach, the proposed approach can improve the pass rate by 57% on average with similar standby power and the same number of body biasing gates. This approach can reduce the standby power, on average, by 84%, with a 20% pass rate loss, more than the approach to bias all the gates.

Runtime noise management systems typically respond to on-chip noise sensors to accurately capture voltage emergencies. As such, the threshold voltage for noise sensors to report emergencies serves as a critical tuning knob between the system failure rate and the runtime performance loss (RPL) due to false alarms. Unfortunately, the problem of optimal threshold voltage computation remains open in literature despite its importance. The problem is further complicated by process variations, which introduce significant variations in load currents and thus in noise across different chips. A uniform noise margin may not work optimally for all the chips. In this paper, we first formulate the problem of minimizing the system failure rate subject to a given RPL constraint. We then put forward a uniform scheme to find an optimal solution for all chips. Compared to a seemingly more intuitive approach which is too conservative, experimental results over a set of industrial designs show an average of 32.1% reduction in system failure rate under the same RPL constraint. We further show that with the help of Iddqmeasurements during testing which reveals process variation information, it is possible and efficient to compute a per-chip optimal threshold voltage. Such an approach further reduces the system failure rate by 25.0% on average compared with the uniform threshold approach, under the same RPL constraint. To the best of the authors knowledge, this is the first in-depth study on optimal threshold voltage computation for noise sensors. We hope that it shall point out new directions for systematic studies of on-chip noise sensor utilization.

The power grid needs to be frequently analyzed during the design process of power distribution network. Hence, an effective method being able to capture its transient behavior is desired for designers.

Rnv8T nonvolatile SRAM combines conventional SRAM and resistive RAM to provide both fast access speed and data retention. Traditional test methods for conventional SRAM or resistive RAM are not suitable for nonvolatile SRAM. This paper analyzes the defective behavior of the Rnv8T nonvolatile SRAM based on defect injection and simulation. Simulation results showed that the inject defects caused stuck-at faults and transition faults which escaped from conventional March tests. Based-on the defective behavior and circuit operations, a straight forward test algorithm is proposed to detect the escaped faults.

This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the 3D stacked ICs (3D-SICs) configuration. Additionally, a serialized compressed signal generator (SCSG) design is also developed of the proposed scheme to generate the corresponding controlled signals for SCSA to ensure the test cost reduction. Experimental results and comparisons show that the proposed scheme can effectively achieve the good performance in test pin count and test time reduction with little extra hardware overhead penalty.

Power integrity is generally considered to be one of the major bottlenecks hindering the prevalence of three-dimensional integrated circuits (3D ICs). The higher integration density and smaller footprint result in significantly increased power density, which threatens the system reliability. In view of this, there has been groundswell of interest in academia to model, design or optimize the power delivery networks (PDNs) in 3D ICs. Unfortunately, while several PDN benchmarks exist for 2D PDNs, none is available in the context of 3D. As a consequence, most existing literature resorts to ad-hoc designs by artificially stacking 2D PDNs for experiments, rendering the results less convincing. In this paper, we put forward a set of ten PDN benchmarks that are extracted from industrial 3D designs. These designs are carefully selected such that they cover a wide range of functionality, size, TSV number, tier number and packaging style. We hope that the released benchmarks can facilitate and promote research in 3D PDNs.

Power supply noise has become one of the primary concerns in low power designs. To ensure power integrity, designers need to make sure that voltage droop and bounce do not exceed noise margin in all possible scenarios. Since it is very difficult to capture the exact worst corner among the mist of complex functionalities in modern VLSI designs, statistical design methodologies have been adapted, which may bring significant design overhead. In view of this, various runtime techniques have been proposed in literature to suppress power grid noise adaptively. This paper first presents various challenges in power grid designs from an industrial perspective, explains the difficulties in handling them at deign time, and then reviews various runtime techniques to adaptively suppress power supply noise, including sensor-based power gating, re-routable decaps, proactive clock frequency actuator, and PLL based clocking.

Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit capacitances have a great effect on reducing ratio mismatch. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuits. The relationship between correlation and variation of capacitance ratio is also presented. Therefore, both mismatch and variation of capacitance ratio can be expressed in terms of capacitance correlation. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed up the time to market.