While LDPC codes have been widely acclaimed in recent years for their near-capacity performance, they have not found their way into many important applications. For some cases, this is due to their increased decoding complexity relative to the classical coding techniques. For other cases, this is due to their inability to reach very low bit error rates (e.g., 10-12) at low signal-to-noise ratios (SNRs), a consequence of the error rate floor phenomenon associated with iterative LDPC decoders. In the present paper, we make strides in the low-floor problem by identifying the weaknesses of the code under study and applying compensatory counter-measures. These counter-measures include: modifying the code itself, modifying the decoder, or adding a properly designed outer algebraic code. Our results demonstrate that each of these techniques can successfully lower an LDPC code's floor, and that, for the code under study, an outer BCH code appears to be particularly effective. All of our results are based on FPGA decoder simulations and so they are reliable and repeatable.

In this letter, we present design techniques for structured irregular repeat-accumulate (S-IRA) codes with low error-rate floors. These S-IRA codes need not be quasi-cyclic, permitting flexibility in code dimension, length, and rate. We present a simple ensemble estimate of the level of the error-rate floor of finite-length IRA codes on the additive white Gaussian noise channel. This performance estimate provides guidance on the choice of IRA code column weights which yield low floors. We also present two design algorithms for S-IRA codes accompanied by software- and hardware-based performance results which demonstrate their low floors. Lastly, we present two design algorithms for multirate S-IRA code families implementable by a single encoder/decoder

In this paper, we present design techniques for structured extended irregular repeat-accumulate (SeIRA) codes with low error-rate floors. These SeIRA codes permit flexibility in code dimension, length, and rate, while facilitating encoder/decoder implementation due to their structure. We present a design algorithm for SeIRA codes and software-based performance results which demonstrate their low floors. Then we present two design algorithms for multi-rate SeIRA code families implementable by a single encoder/decoder. Lastly, we present the performances of SeIRA codes on the single-carrier independent Rayleigh fading channel and SeIRA-coded OFDM over a frequency-selective correlated fading channel

In a recent paper, Yang et al. presented the class of extended irregular repeat-accumulate (eIRA) codes which are efficiently encodable LDPC codes possessing very low error-rate floors and are appropriate for code rates 1/2 or greater. While efficiently encodable, the left-most (n-k)-by-k submatrix of an eIRA code parity-check matrix is random in nature, making efficient decoder implementation problematic. In the present paper, we present structured eIRA codes. We first present some ensemble results for the general class of eIRA codes, after which the subclass of structured eIRA (SeIRA) codes is defined. Software- and hardware-based performance results for SeIRA code designs (rates 0.5 to 0.9) are then presented.