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Sotirios Matakias

dblp:55/6451 · DBLP profile ↗
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5ranked-venue papers
4as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 4 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 46% Integrated circuit design · 30% Electronic design automation · 23%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › static analysis
code checker		 0.112008
A Current Mode, Parallel, Two-Rail Code Checker · IEEE Trans. Computers 2008
Integrated circuit design
digital circuit design		 0.112008
A Current Mode, Parallel, Two-Rail Code Checker · IEEE Trans. Computers 2008
Hardware reliability and fault tolerance
error detection		 0.112008
A Current Mode, Parallel, Two-Rail Code Checker · IEEE Trans. Computers 2008
Hardware reliability and fault tolerance › fault-tolerant design › fault-tolerant circuit design
two-rail code checker		 0.112008
A Current Mode, Parallel, Two-Rail Code Checker · IEEE Trans. Computers 2008
Integrated circuit design › analog and mixed-signal circuits › analog circuit design
current-mode circuits		 0.012008
A Current Mode, Parallel, Two-Rail Code Checker · IEEE Trans. Computers 2008

Methods — techniques the papers use, named apart from their topics

electrical simulation · 0.1circuit design · 0.1
YearPublicationVenuePosition
2015 A current monitoring technique for IDDQ testing in digital integrated circuits
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
 Integr.1
2008 A Current Mode, Parallel, Two-Rail Code Checker
abstract
A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for the implementation of high fan-in embedded checkers, is presented. The new checker is characterised by high testability, high speed operation and low silicon area requirements. The circuit has been designed, for various fan-in values, in a 0.18 mum technology and electrical simulations have been carried out to validate its operation, considering process, power supply and temperature variations as well as variations of the electrical parameters.
Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
 IEEE Trans. Computers1
2005 Fast, Parallel Two-Rail Code Checker with Enhanced Testability
abstract
A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for high n-variable (high fan-in) implementations, is presented. The checker is characterized by high testability, high operating frequencies and low silicon area requirements. The circuit has been designed, for various n-variable values, in a 0.18/spl mu/m technology and SPICE simulations have been carried out to validate its operation.
Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
 IOLTS1
2004 A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
 J. Electron. Test.1
2003 A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs
abstract
We propose a new concurrent soft and timing error detection circuit that exploits the time redundancy approach to achieve tolerance with respect to transient and delay faults. The idea is based on current mode sense amplifier topologies to provide fast error detection times.
Yiorgos Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Themistoklis Haniotakis
 IOLTS2