VLDB 2026 Research / reviewers in the wild / expert
WeiDong Hu
dblp:55/7417
· DBLP profile ↗
7ranked-venue papers
3as first author
0since 2021 · last 2013
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Graphics, computer vision, multimedia, augmented reality and games · 5 · 2 first-authorArtificial intelligence and machine learning · 1Computer networks · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
1 paper |
Coding theory · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 100% | |
| Computer graphics and multimedia
1 paper |
Image and video coding · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
parallel algorithms |
0.1 | 1 | 2012 | Highly Scalable Parallel Arithmetic Coding on Multi-Core Processors Using LDPC Codes · IEEE Trans. Commun. 2012 |
Coding theory › error-correcting codes
LDPC codes |
0.1 | 1 | 2012 | Highly Scalable Parallel Arithmetic Coding on Multi-Core Processors Using LDPC Codes · IEEE Trans. Commun. 2012 |
Coding theory › source coding › multiterminal source coding › distributed source coding
slepian-wolf coding |
0.1 | 1 | 2012 | Highly Scalable Parallel Arithmetic Coding on Multi-Core Processors Using LDPC Codes · IEEE Trans. Commun. 2012 |
Coding theory › source coding › entropy coding
arithmetic coding |
0.0 | 1 | 2012 | Highly Scalable Parallel Arithmetic Coding on Multi-Core Processors Using LDPC Codes · IEEE Trans. Commun. 2012 |
Coding theory
source coding |
0.0 | 1 | 2012 | Highly Scalable Parallel Arithmetic Coding on Multi-Core Processors Using LDPC Codes · IEEE Trans. Commun. 2012 |
Image and video coding
multiview video coding |
0.0 | 1 | 2009 | Adaptive data-driven parallelization of multi-view video coding on multi-core processor · Sci. China Ser. F Inf. Sci. 2009 |
Methods — techniques the papers use, named apart from their topics
LDPC-based Slepian-Wolf coding · 0.3multi-core processor scheduling · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Comparisons reducing for local stereo matching using hierarchical structureabstractWe propose a method for local stereo matching that reduces the number of matching comparisons, which also reduces the running time. By using hierarchical structure with suitable disparity candidate set, the proposed method maintains accuracy of local matching methods. Theoretical analysis and experimental results show that the number of comparisons of the proposed method is independent of the disparity range, while the accuracy is nearly the same as the corresponding local method. WeiDong Hu, Kang Zhang 0004, Lifeng Sun, Shiqiang Yang |
ICME | 1 |
| 2012 | Binary stereo matching
Kang Zhang 0004, Jiyang Li, WeiDong Hu, Lifeng Sun, Shiqiang Yang |
ICPR | 4 |
| 2012 | Highly Scalable Parallel Arithmetic Coding on Multi-Core Processors Using LDPC CodesabstractWe describe a highly scalable parallel arithmetic coder for Markov inputs suitable for implementation on modern multi-core processors. The algorithm divides the input into interleaved sub-sequences which can be then processed independently on different processing units using LDPC-based Slepian-Wolf coding. Experimental simulations show good scalability of the proposed algorithm while also maintaining good compression performance. Notably, when compared with traditional parallel arithmetic coding, the proposed method maintains a much higher efficiency both respect to the entropy limit as well as in terms of the ability to distribute computations across multiple cores without performance loss. WeiDong Hu, Jiangtao Wen, Weiyi Wu, Yuxing Han 0001, Shiqiang Yang, John D. Villasenor |
IEEE Trans. Commun. | 1 |
| 2011 | Virtual support window for adaptive-weight stereo matchingabstractIt attracts many researchers' attention to find a stereo matching algorithm both accurate and fast. Yoon and Kweon's Adaptive Support-Weight(ASW) method is supposed to be a very successful algorithm in both accuracy and speed. However, it is very time consuming for ASW to take a large number of pixels into consideration for computing a disparity. In this paper, we present a stereo matching algorithm based on the ASW method to solve this problem. We introduce a time efficient technique, partial sum, to reduce the information of pixels in a large window into a small one so that disparities can be computed using the large window of pixels with low time complexity. Our method can obtain better representation of local properties of a pixel than the ASW method. Experimental results show that our method produces more accurate disparity maps than ASW method. WeiDong Hu, Kang Zhang 0004, Lifeng Sun, Jiyang Li, Shiqiang Yang |
VCIP | 1 |
| 2009 | Frame-level heuristic scheduling Multi-view Video Coding on symmetric multi-core architectureabstractIn this paper, we propose a frame-level heuristic scheduling parallel emerging Multi-view Video Coding (MVC) using Directed Acyclic Graph (DAG) on Intel multi-core processor. We illustrate the reason to choose heuristic scheduling and formulate the problem. Through defining dependent degree and concurrent degree, we demonstrate why to choose frame as parallel granularity. Experimental results demonstrate the effectiveness and scalability of our parallel MVC. Yi Pang, Jiangtao Wen, Lifeng Sun, WeiDong Hu, Shiqiang Yang |
ICIP | 4 |
| 2009 | Adaptive data-driven parallelization of multi-view video coding on multi-core processor
Yi Pang, WeiDong Hu, Lifeng Sun, Shiqiang Yang |
Sci. China Ser. F Inf. Sci. | 2 |
| 2009 | A Framework for Heuristic Scheduling for Parallel Processing on Multicore Architecture: A Case Study With Multiview Video CodingabstractIn this paper, using the Intel multicore architectures and the emerging multiview video coding standard, we introduce a framework for performing analysis, simulation, and evaluation of heuristics scheduling algorithms for implementing computationally intensive algorithms on multicore processors. The framework allows for accurate and quantitative characterization of the performance of dynamic scheduling algorithms for multimedia applications on different multicore processors without actual implementation of the scheduling algorithm and application on the actual platform. Experimental results demonstrate the effectiveness and scalability of our framework. Yi Pang, Lifeng Sun, Jiangtao Wen, Fengyan Zhang, WeiDong Hu, Shiqiang Yang |
IEEE Trans. Circuits Syst. Video Technol. | 5 |