The Computing-In-Memory (CIM) paradigm offers a promising solution to the memory-wall bottleneck that limits conventional Von Neumann architectures. By performing data processing at the same physical location where the data are stored, CIM-based architectures minimize costly data movement and drastically improve energy efficiency. When implemented with Ferroelectric Field Effect Transistors (FeFETs), additional advantages from the non-volatility, fast switching, and low operating voltage of FeFETs are added. However, the widespread adoption of FeFETs is limited by their poor endurance, which is overcome by a Back End of the Line (BEoL) integration of FeFET-2, where a ferroelectric capacitor (FeCAP) is wired to the gate of a CMOS transistor providing high endurance compatible with low-power edge applications. These properties enable dense, low-power, and high-speed matrix operations essential for AI workloads. As a result, FeFET-2-based CIM accelerators offer a promising solution for energy-efficient, high-performance AI at the edge. The Ferro4EdgeAI project aims to develop an ultra low-power, scalable edge accelerator for AI, targeting a significant gain in energy efficiency with respect to state-of-the-art AI hardware accelerators. To attain this, our project focuses on innovation all along the value chain from materials, physic concepts, device architecture, integration technologies, and accelerators in a holistic design space exploration approach.

Ferroelectric memory devices have emerged as a promising class of non-volatile memory technologies, offering a unique combination of high-speed operation, low power consumption, and good endurance compared to conventional flash memory. These devices leverage the bistable polarization states of ferroelectric materials to store data, enabling nonvolatile retention while maintaining fast read/write capabilities. The discovery of hafnium-based ferroelectric materials that are fully CMOS compatible and exhibit robust ferroelectricity at nanoscale dimensions has further enhanced their integration and scalability potential. For IoT devices, which require non-volatile state retention under constrained power budgets and frequent interruptions, we propose a novel FeAND memory cell designed to serve as a non-volatile backup for volatile memory. Unlike conventional ferroelectric memories that rely on current sensing, our design directly outputs a voltage signal, eliminating the need for sensing circuits. The cell exhibits a logical AND-like behavior, enabled by an innovative read scheme based on a CMOS inverter. The cell can function as both a non-volatile memory element and a logic gate where one input is permanently stored as a polarization state. This dual functionality enables novel Computing-in-Memory architectures by embedding logic operations directly within the memory array. We validate our design using Cadence Spectre simulations with the GlobalFoundries 28SLP technology.

The promising features introduced by the integration of ferroelectric devices into conventional integrated circuit fabrication processes have spurred extensive research into device reliability, non-volatile memory circuits and system-level applicability. Their low-power operation makes them particularly suitable for Internet of Things applications, and their intrinsic memory properties position them as strong candidates for nonvolatile memory technologies and In-memory Computing. For such data-intensive applications, the need to ensure secure data storage, processing and transmission has motivated the adaptation of classic hardware security strategies to this emerging inmemory computing paradigm, demonstrating high effectiveness with ferroelectric designs. However, a variability analysis from a design perspective remains unexplored towards either implementing security primitives based on identity, e.g. Physical Unclonable Functions, or based on stochasticity, e.g. True Random Number Generators.In this work, we focus on the variations expected in a commercial 28 nm process and its compatibility with memory cell design, in view of the implementation of a Physical Unclonable Function in a ferroelectric memory array. In particular we show that while obtaining a sufficient output variability, which can be used for fingerprinting the device, a fair current ratio is maintained, allowing memory array implementations.

Non-volatile in-memory computing (iMC) has emerged as an energy-efficient paradigm well suited to AI workloads. Its implementation using 1T1C FeMFETs (Ferroelectric Memory Field Effect Transistors), a best-in-class emerging nonvolatile memory technology that integrates BEOL ferroelectric devices with FEOL transistors, is of particular interest. This interest stems from their potential to enable large-scale multiplyaccumulate (MAC) operations in both digital and analog domains. However, realizing tangible performance benefits requires comprehensive cross-layer exploration of both design and technology parameters, extending up to accelerator level. In this work, we propose a bitcell-level multi-objective optimization methodology to identify and extract optimal sizing solutions that provide tractable trade-offs between key performance indicators (KPI). We further demonstrate how this approach facilitates cross-stack exploration of accelerator architectures. Results are presented as Pareto fronts spanning $2-4 \mathrm{KPIs}$: a $2-\mathrm{KPI}$ problem illustrates the methodology, while a $\mathbf{4}$-KPI problem represents a realistic design scenario. Comparison is made between $\mathbf{1 3 0} \mathbf{n m}$ and 28 nm technologies demonstrating a decrease in the average of write energy and area up to 24 X and 30 X respectively.

This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and ultra-efficient class of ANN accelerators, the neural network compute cube$(N^{2}C^{2})$, which is specifically designed to execute complex machine learning tasks in a 3D technology, in order to provide the high computing power and ultra-high efficiency needed for future edgeAI applications. We showcase its effectiveness by targeting the challenging class of Transformer ANNs, tailored for Automatic Speech Recognition and Machine Translation, the two fundamental components of speech-to-speech translation. To gain the full benefit of the accelerator design, we develop disruptive vertical transistor technologies and execute design-technology-co-optimization (DTCO) loops from single device, to cell and compute cube level. Further, a hardware-software-co-optimization is executed, e.g. by compressing the executed speech recognition and translation models for energy efficient executing without substantial loss in precision.

In the contemporary security landscape, the incorporation of photonics has emerged as a transformative force, unlocking a spectrum of possibilities to enhance the resilience and effectiveness of security primitives. This integration represents more than a mere technological augmentation; it signifies a paradigm shift towards innovative approaches capable of delivering security primitives with key properties for low-power systems. This not only augments the robustness of security frameworks, but also paves the way for novel strategies that adapt to the evolving challenges of the digital age. This paper discusses the security layers and related services that will be developed, modeled, and evaluated within the Horizon Europe NEUROPULS project. These layers will exploit novel implementations for security primitives based on physical un-clonable functions (PUFs) using integrated photonics technology. Their objective is to provide a series of services to support the secure operation of a neuromorphic photonic accelerator for edge comnuting applications.

The vertical nanowire field effect transistor (VN-WFET) is an emerging technology that promises to improve the sustainability of future transistor scaling beyond the limitations of conventional lateral devices. With its 3D gate-all-around (GAA) architecture, such a technology enables designs with improved energy-efficiency as well as reduced footprint and thus interconnect capacitance. In this work, and based on the compact model of a real VNWFET device, we present the design flow for the generation of a standard cell library starting from the circuit and physical design of logic cells to logic synthesis based on the VNWFET technology. The results on the synthesized benchmark cells, as compared against 45nm and 65nm CMOS libraries, demonstrate a significant decrease in the average dynamic power consumption and delay values up to 71X and 34X respectively, with anaveragearea gain of up to 5X. However, an increase in leakage power consumption (up to 2X on average) was also observed.

Static Random Access Memories (SRAM) are fast and efficient circuits used as the main working memory of processing units. However, associating these volatile memories with external non-volatile memories leads to energy consumption and area penalties, while leading to security issues. Ferroelectric-based NVSRAMs are one of the most promising ways of combining the high efficiency of SRAMs with non-volatile operations to tackle these challenges. In this work, several design parameters of the bitcell are optimized to ensure error-less data transfer between 6T SRAM internal nodes and 4 ferroelectric capacitors (4C). The presented 6T4C bitcell presents STORE and RECALL energies of 161fJ/bit and 27fJ/bit, respectively, and STORE and RECALL times of 480ns and 245ns, respectively. A high reliability is achieved from −40°C to +85°C for SS, TT and FF fabrication corners. The integration of the four FeCAPs in the bitcell leads to a 46% area overhead, a 94% WRITE time degradation, and a 32% WRITE energy increase. However, an increase of less than 0.5% in both READ time and energy has been observed. A previously developed Fast-Erase system has also been integrated for countering cold-boot attacks. Combining design optimizations and Fast-Erase technique ensures cold-boot attack immunity of the memory and enables error-less RECALL with WRITE operations between STORE and RECALL, leading to new use-cases of NVSRAM circuits.

This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases.

Data-centric applications such as Artificial Intelligence and IoT are putting stringent performance and energy efficiency constraints on hardware implementations of computing architectures. Computing in Memory paradigm appears as a viable approach to to address such constraints and ferroelectric FETs (FeFETs) push this paradigm at a finer grain by enabling the design of true non-volatile logic gates, by implementing tight combination of memory and logic called Logic-in-Memory (LiM). From the basic non-volatile logic gate design up to the application-level evaluation, several challenges have to be addressed.In this paper, we present a methodology to design complex operations such as cryptographic operations using FeFET, integrate them into a complete computing architecture and evaluate its benefits. Current challenges related to logic synthesis and tools for synthesis of these LiM structures will also be discussed.

In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior is turned into a design implementation in terms of logic gates. Historically, logic synthesis was tightly related to the physical implementation of the logic gates. Nowadays, pushed by the forecasted end of Moore's law, several emerging technologies (e.g., nanodevices, optical computing, quantum computing) are candidates to either replace or co-exist with the de facto standard CMOS technology. The main consequence of the rising of those emerging technologies is that the logic synthesis has to face new issues and, at the same time, exploits new opportunities. The goal of this paper is thus to present three emerging technologies (Vertical Nanowire Field Effect Transistors, Ferroelectric Transistors, and Memristors), how to use them to implement logic gates, and the main challenges and issues for the logic synthesis.

Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices., which are well suited to pursue scaling beyond lateral scaling limitations around 7nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model., which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50nm. We used this model to simulate the projected performance of inverter logic gates based on passive load., active load and complementary topologies and carry out an performance exploration for the number of nanowires in transistors. In terms of compactness., through a dedicated full 3D layout design., we also demonstrate a 48% reduction in lateral dimensions for the complementary structure with respect to 7nm FinFET-based inverters.

Edge computing requires highly energy efficient microprocessor units with embedded non-volatile memories to process data at IoT sensor nodes. Ferroelectric non-volatile memory devices are fast, low power and high endurance, and could greatly enhance energy-efficiency and allow flexibility for finer grain logic and memory. This paper will describe the basics of ferroelectric devices for both hysteretic (non-volatile memory) and negative capacitance (steep slope switch) devices, and then project how these can be used in low-power logic cell architectures and fine-grain logic-in-memory (LiM) circuits.

Today, life is becoming increasingly connected. From TVs to smartphones, including vehicles, buildings, and household appliances, everything is interconnected in what we call the “Internet of Things” (IoT). IoT is now part of our life and we have to deal with it. More than ten billion devices are already connected and five times more are expected to be deployed in the next five years. While deployment and integration of IoT is expanding, one of the main challenge is to provide practical solutions to security, privacy, and trust issues in IoT. Protection and security mechanisms need to include features such as interoperability and scalability but also traceability, authentication, and access control while remaining lightweight. Among the most promising approaches to such security mechanisms, physical unclonable functions (PUFs) provide a unique identifier for similar but different integrated circuits using some of their physical characteristics. These types of functions can thus be used to authenticate integrated circuits, provide traceability and access control. This paper presents a comprehensive case study of the transient effect ring oscillator (RO) PUF from its implementation on FPGAs to its complete characterization. The implementation of the PUF is detailed for two different families of FPGAs: 1) Xilinx Spartan 6 and 2) Altera Cyclone V. All the metrics used for the characterization are explained in detail and the results of the characterization include robustness to environmental parameters including variations in temperature and voltage. Finally, we compare our results with those obtained for another PUF: the RO PUF. All the design files are available online to ensure repeatability and enable comparison of our contribution with other studies.

Physical unclonable functions (PUF) are a promising approach in design for trust and security. A PUF derives a unique identifier using physical characteristics of different dies containing an identical circuit, so it can be used to authenticate chips and for identification. The transient effect ring oscillator (TERO) PUF is based on the extraction of entropy due to process variations by comparing TERO cells characteristics. The TERO cell is designed and implemented with a symmetric structure that requires special selection of the gates used and the delays of all connections inside the cell. Implementing this cell in FPGAs is challenging because the structure of FPGAs does not automatically allow designers to choose connections between elements. However, by manually specifying constraints and using specific features of the target FPGA family, the symmetry of the TERO cell can be established and reproduced in larger designs. In this work, the design of the TERO cell is described for two different FGPA technologies (45nm Xilinx Spartan 6 and 28nm Altera Cyclone V). The statistical characterization of the TERO-PUF with the two targeted FPGAs has resulted in a uniqueness of 48.46% with Spartan 6 and 47.62% with Cyclone V. The result for the steadiness is 2.63% with Spartan 6 and 1.8% with Cyclone V. These results are close to the results obtained by several works that use ring oscillator RO-PUF which are considered the best candidate for PUF implementation on FPGAs. However, TERO-PUF is less sensitive to electromagnetic analysis than RO-PUF. Additionally, unlike RO-PUF, TERO-PUF is able to generate multiple bits per challenge (from one to three) and we have shown during the statistical characterization that the TERO-PUF provides from 0.85 to 1 bits of entropy per response bit.

This paper proposes a theoretical study and a full overview of the design, evaluation, and optimization of a PUF based on transient element ring oscillators (TERO-PUF). We show how, by following some simple design rules and strategies, designers can build and optimize a TERO-PUF with the state-of-the-art PUF characteristics in a standard CMOS technology. To this end, we analyzed the uniqueness, steadiness, and randomness of responses generated from 30 test chips in a CMOS 350-nm process in nominal and corner voltage and temperature conditions. Response generation schemes are proposed and discussed to optimize the PUF performances and reduce its area without noticeable loss in its output quality. In particular, we show that the large area of the basic blocks in the TERO-PUF is balanced by the high level of entropy extracted in each basic block. Guidelines are provided to balance reliability and randomness of the responses and the design area.