This workshop will teach instructors how to incorporate Machine Learning into their mobile course using ML Kit for Firebase. ML Kit provides powerful machine learning functionality to your app running either iOS or Android and is for both experienced and novice machine learning developers. With just a few lines of code, you can use these powerful and easy to use machine learning packages. This workshop will focus on using machine learning in mobile applications to solve real-world problems.

This workshop will teach instructors how to incorporate Machine Learning into their mobile course using ML Kit for Firebase. ML Kit provides powerful machine learning functionality to your app running either iOS or Android and is for both experienced and novice machine learning developers. With just a few lines of code, you can use these powerful and easy to use machine learning packages. This workshop will focus on using machine learning in mobile applications to solve real-world problems.

This workshop will teach instructors how to incorporate Machine Learning into their mobile course using ML Kit for Firebase. ML Kit provides powerful machine learning functionality to your app running either iOS or Android and is for both experienced and novice machine learning developers. With just a few lines of code, you can use these powerful and easy-to-use machine learning packages. This workshop will focus on using machine learning in mobile applications to solve real-world problems.

Version control software, such as Git, is commonly used in Computer Science courses. Often students simply learn a few commands to submit an assignment without really understanding how the advanced features work and the benefits of version control. This research investigates the impact of introducing a Git tutorial in an introductory full-stack Web Development course. The semester with the tutorial intervention is compared to a previous semester with no tutorial intervention. The research consists of a survey at the beginning and end of the semester. From the surveys, we observe that students' perceptions of major Git concepts increased in both semesters. Also, when introducing a lightweight intervention of a tutorial, students' perceptions of concepts of how and why to create a branch in Git improve in a statistically significant manner. This research provides preliminary evidence that using lightweight interventions in assignments to engage students with tooling without reducing instructional time on other course concepts can encourage learning and usage of advanced tool features.

This workshop will teach instructors how to incorporate Machine Learning into their mobile course using ML Kit for Firebase. ML Kit provides powerful machine learning functionality to your app running either iOS or Android and is for both experienced and novice machine learning developers. With just a few lines of code, you can use these powerful and easy to use machine learning packages. This workshop will focus on using machine learning in mobile applications to solve real-world problems. In this workshop, we will explore some of the functionality ML Kit provides. Topics include text recognition, facial detection, recognizing points of interest, image characterization, and labeling. We will integrate a few of these features into fully functional apps running on iOS or Android. Additionally, we will explore tradeoffs between executing ML Kit in the cloud and on a device. This workshop is targeted for instructors teaching a web development or mobile application course looking to incorporate cloud and native ML functionality. It is also suited for anyone wanting to deploy ML applications quickly using a feature-rich API. A laptop running Android Studio or Xcode is required. Prior to the workshop participants will be given instructions for software installation.

This workshop will show how web development skills can be used to develop native mobile apps (iOS, Android, and Web) using a JavaScript library called React Native, an open-source framework developed by Facebook. React Native extends the popular React web framework with support for truly native mobile apps. After completing the workshop, participants will have a classroom-ready assignment to share with their students.

This workshop will teach instructors how to incorporate Machine Learning into their mobile course using ML Kit for Firebase. ML Kit provides powerful machine learning functionality to your app running either iOS or Android and is for both experienced and novice machine learning developers. With just a few lines of code, you can use these powerful and easy to use machine learning packages. This workshop will focus on using machine learning in mobile applications to solve real-world problems.

This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs between the placement of protocol handling functions in programmable logic and on an embedded processor is demonstrated. This is facilitated by two new design tool capabilities: first, being able to describe programmable logic based functions in a more software-like manner; and second, being able automatically to generate efficient interfaces between a programmable logic fabric and an embedded processor. The methodology is illustrated by an example of a simple Web server, targeted at Xilinx Virtex-II Pro and Virtex-4 platform FPGAs. Trade-offs both of complete protocol placement and of within-protocol placement are systematically investigated in terms of resources used and packet handling latency. The work points the way to highly fluid allocation of functions to implementations, beyond conventional static codesign.

Software-based network intrusion detection systems (NIDS) often fail to keep up with high-speed network links. In this paper an FPGA-based pre-filter is presented that reduces the amount of traffic sent to a software-based NIDS for inspection. Simulations using real network traces and the Snort rule set show that a pre-filter can reduce up to 90% of network traffic that would have otherwise been processed by Snort software. The projected performance enables a computer to perform real-time intrusion detection of malicious content passing over a 10 Gbps network using FPGA hardware that operates with 10 Gbps of throughput and software that needs only to operate with 1 Gbps of throughput.

This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs between the placement of protocol handling functions in programmable logic and on an embedded processor is demonstrated. This is facilitated by two new design tool capabilities: first, being able to describe programmable logic based functions in a more software-like manner; and second, being able automatically to generate efficient interfaces between a programmable logic fabric and an embedded processor. The methodology is illustrated by an example of a simple web server, targeted at Xilinx Virtex-II Pro or Virtex-4 FX platform FPGAs. Trade-offs both of complete protocol placement and of within-protocol placement are systematically investigated in terms of resources used and packet handling latency. This provides an excellent range of service times, corresponding to differing logic fabric and memory resource requirements. The work points the way to highly fluid allocation of functions to implementations, beyond conventional static codesign.

No abstract available.

Internet protocol (IP) address lookup is a central processing function of Internet routers. While a wide range of solutions to this problem have been devised, very few simultaneously achieve high lookup rates, good update performance, high memory efficiency, and low hardware cost. High performance solutions using content addressable memory devices are a popular but high-cost solution, particularly when applied to large databases. We present an efficient hardware implementation of a previously unpublished IP address lookup architecture, invented by Eatherton and Dittia (see M.S. thesis, Washington Univ., St. Louis, MO, 1998). Our experimental implementation uses a single commodity synchronous random access memory chip and less than 10% of the logic resources of a commercial configurable logic device, operating at 100 MHz. With these quite modest resources, it can perform over 9 million lookups/s, while simultaneously processing thousands of updates/s, on databases with over 100000 entries. The lookup structure requires 6.3 bytes per address prefix: less than half that required by other methods. The architecture allows performance to be scaled up by using parallel fast IP lookup (FIPL) engines, which interleave accesses to a common memory interface. This architecture allows performance to scale up directly with available memory bandwidth. We describe the tree bitmap algorithm, our implementation of it in a dynamically extensible gigabit router being developed at Washington University in Saint Louis, and the results of performance experiments designed to assess its performance under realistic operating conditions.

A suite of tools called NCHARGE (Networked Configurable Hardware Administrator for Reconfiguration and Governing via End-systems) has been developed to simplify the co-design of hardware and software components that process packets within a network of Field Programmable Gate Arrays (FPGAs). A key feature of NCHARGE is that it provides a high-performance packet interface to hardware and standard Application Programming Interface (API) between software and reprogrammable hardware modules. Using this API, multiple software processes can communicate to one or more hardware modules using standard TCP/IP sockets. NCHARGE also provides a Web-Based User Interface to simplify the configuration and control of an entire network switch that contains several software and hardware modules.

Continuing growth in optical link speeds places increasing demands on the performance of Internet routers, while deployment of embedded and distributed network services imposes new demands for flexibility and programmability. IP address lookup has become a significant performance bottleneck for the highest performance routers. Amid the vast array of academic and commercial solutions to the problem, few achieve a favorable balance of performance, efficiency, and cost. New commercial products utilize content addressable memory (CAM) devices to achieve high lookup speeds at an exorbitantly high hardware cost with limited flexibility. In contrast, this paper describes an efficient, scalable lookup engine design, able to achieve high performance with the use of a small portion of a reconfigurable logic device and a commodity random access memory (RAM) device. The Fast Internet Protocol Lookup (FIPL) engine is an implementation of Eatherton and Dittia's previously unpublished Tree Bitmap algorithm (1998) targeted to an open-platform research router. FIPL can be scaled to achieve guaranteed worst-case performance of over 9 million lookups per second with a single SRAM operating at the fairly modest clock speed of 100 MHz. Experimental evaluation of FIPL throughput, latency, and update performance is provided using a sample routing table from Mae West.