Demo Data from VLDB 2026 / reviewers in the wild / expert
Michael Kurth
dblp:55/9843
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
2 papers |
Hardware security and side channels · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels › microarchitectural attacks
cache attacks |
0.4 | 1 | 2020 | : Practical Cache Attacks from the Network · SP 2020 |
Hardware security and side channels
microarchitectural attacks |
0.4 | 1 | 2020 | : Practical Cache Attacks from the Network · SP 2020 |
Hardware security and side channels
microarchitectural side channel |
0.4 | 1 | 2020 | ABSynthe: Automatic Blackbox Side-channel Synthesis on Commodity Microarchitectures · NDSS 2020 |
Methods — techniques the papers use, named apart from their topics
fuzzing · 0.9black-box analysis · 0.9reverse engineering · 0.4prime+probe · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | ABSynthe: Automatic Blackbox Side-channel Synthesis on Commodity Microarchitectures
Ben Gras, Cristiano Giuffrida, Michael Kurth, Herbert Bos, Kaveh Razavi |
NDSS | 3 |
| 2020 | : Practical Cache Attacks from the NetworkabstractIncreased peripheral performance is causing strain on the memory subsystem of modern processors. For example, available DRAM throughput can no longer sustain the traffic of a modern network card. Scrambling to deliver the promised performance, instead of transferring peripheral data to and from DRAM, modern Intel processors perform I/O operations directly on the Last Level Cache (LLC). While Direct Cache Access (DCA) instead of Direct Memory Access (DMA) is a sensible performance optimization, it is unfortunately implemented without care for security, as the LLC is now shared between the CPU and all the attached devices, including the network card.In this paper, we reverse engineer the behavior of DCA, widely referred to as Data-Direct I/O (DDIO), on recent Intel processors and present its first security analysis. Based on our analysis, we present NetCAT, the first Network-based PRIME+PROBE Cache Attack on the processor's LLC of a remote machine. We show that NetCAT not only enables attacks in cooperative settings where an attacker can build a covert channel between a network client and a sandboxed server process (without network), but more worryingly, in general adversarial settings. In such settings, NetCAT can enable disclosure of network timing-based sensitive information. As an example, we show a keystroke timing attack on a victim SSH connection belonging to another client on the target server. Our results should caution processor vendors against unsupervised sharing of (additional) microarchitectural components with peripherals exposed to malicious input. Michael Kurth, Ben Gras, Dennis Andriesse, Cristiano Giuffrida, Herbert Bos, Kaveh Razavi |
SP | 1 |