Demo Data from VLDB 2026 / reviewers in the wild / expert
Panagiotis Linardis
dblp:56/284
· DBLP profile ↗
7ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Databases, data management, data science and information retrieval · 3Software engineering, systems software and programming languages · 2Theory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 1 | 2003 | Accelerating the compaction of test sequences in sequential circuits through problem size reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Electronic design automation › hardware verification and test › test compaction
test sequence compaction |
0.0 | 1 | 2003 | Accelerating the compaction of test sequences in sequential circuits through problem size reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Methods — techniques the papers use, named apart from their topics
heuristic · 0.0branch-and-bound · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering TechniquesabstractThe test sequence compaction problem is modelled here, as a set covering problem. This formulation enables the straightforward application of set covering methods for compaction. Because of the complexity inherent in the first model, a second more efficient, formulation is proposed where the test sequences are modelled as matrix columns with variable costs (number of vectors). Further, matrix reduction rules appropriate to the new formulation, which do not affect the optimality of the solution, are introduced. Finally, the reduced problem is minimized with a branch & bound algorithm. Experiments on a large number of test sets show significant reductions to the original problem by simply using the presented reduction rules. Experimental results comparing our method with others form the literature and also with the absolute minima of the examples, computed separately with the MINCOV algorithm, support the potential of the proposed approach. Michael G. Dimopoulos, Panagiotis Linardis |
DATE | 2 |
| 2003 | Accelerating the compaction of test sequences in sequential circuits through problem size reductionabstractThe problem of compacting a set of test sequences for sequential circuits is modeled here with the help of a covering matrix, where the test sequences are modeled as columns with variable cost to reflect the cost (number of vectors) of covering selected subsets of circuit faults. From this formulation, reduction rules are extracted, particular to this type of problem which, iteratively applied, result in a significant reduction of the size of the initial compaction problem. A characteristic of the reduction rules is that their application will not compromise the optimum solution of the problem. The remaining reduced problem is then solved by a combination of a heuristic and an exact branch and bound algorithm. Experimental results using the above reduction rules show that the sizes of the given sets of test sequences are often significantly reduced and many times these rules directly produce the absolute minimum of the solution. The final results, compared with others from the literature and also with the absolute minima of the examples, computed separately, support the potential of the proposed approach. Michael G. Dimopoulos, Panagiotis Linardis |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 1998 | Comparison of Signature File Models with Superimposed Coding
Dimitrios Dervos, Yannis Manolopoulos, Panagiotis Linardis |
Inf. Process. Lett. | 3 |
| 1997 | S-Index: a Hybrid Structure for Text Retrieval
Dimitrios Dervos, Panagiotis Linardis, Yannis Manolopoulos |
ADBIS | 2 |
| 1994 | Binary ranking for the signature file method
Dimitrios Dervos, Panagiotis Linardis, Yannis Manolopoulos |
Inf. Softw. Technol. | 2 |
| 1994 | Ranking the Validity of Block Candidacies in Signature Files
Dimitrios Dervos, Yannis Manolopoulos, Panagiotis Linardis |
Inf. Sci. | 3 |
| 1986 | Study of a class of conflict resolution strategies for synchronous multiprocessor interconnection networks
Andreas S. Pomportsis, Panagiotis Linardis, Constantin Halatsis |
Microprocessing and Microprogramming | 2 |