In a memory using shuffle interconnections, the concept of sequential accessing in unit time has been related to the existence of a sequence of operations, called a tour, that moves each datum through the read/write port. For memories of size 32, it has been stated that for certain operations no tours exist at window 1; moreover, the existence and construction of tours at other windows and for larger memories have been left as open questions. In this paper, we present several processes for random and sequential accessing, together with their mathematical properties. Furthermore, we give the complete tour structure for all memories of size 2r, 2 ≤ r ≤ 6. Finally, we show how to obtain tours on a memory of size 256 from tours on a memory of size 16.