In 2008-2011 Forsyth County, North Carolina (NC) experienced a four-fold increase in syphilis rising to over 35 cases per 100,000 mirroring the 2021 state syphilis rate. Our methodology extends current models with: 1) donut geomasking to enhance resolution while protecting patient privacy; 2) a moving window uniform grid to control the modifiable areal unit problem, edge effect and remove kriging islands; and 3) mitigating the "small number problem" with Uniform Model Bayesian Maximum Entropy (UMBME). Data is 2008-2011 early syphilis cases reported to the NC Department of Health and Human Services for Forsyth County. Results were assessed using latent rate theory cross validation. We show combining a moving window and a UMBME analysis with geomasked data effectively predicted the true or latent syphilis rate 5% to 26% more accurate than the traditional, geopolitical boundary method. It removed kriging islands, reduced background incidence rate to 0, relocated nine outbreak hotspots to more realistic locations, and elucidated hotspot connectivity producing more realistic geographical patterns for targeted insights. Using the Forsyth outbreak as a case study showed how the outbreak emerged from endemic areas spreading through sexual core transmitters and contextualizing the outbreak to current and past outbreaks. As the dynamics of sexually transmitted infections spread have changed to online partnership selection and demographically to include more women, partnership selection continues to remain highly localized. Furthermore, it is important to present methods to increase interpretability and accuracy of visual representations of data.

This paper describes the test and measurement of high-frequency analog/RF cores in a mixed-signal system-on-chip (SoC) environment using an embedded tester core. A new test methodology has been developed in which high-frequency tests are performed on-chip, but the control and test results are transmitted over the lower bandwidth connectivity associated with the SoC I/O terminals. A low-frequency analog signal is used to modulate a high-frequency squarewave and the resulting waveform is applied to a high-frequency circuit-under-test (CUT) as a test stimulus. The CUT's response is sampled using a coherent subsampling technique and the captured samples are transmitted at low-speeds off-chip from the SoC. A coupled phase-locked-loop and delay- locked-loop structure is employed to generate test waveforms in the 2.7-GHz range and to support high-resolution sampling with a sampling resolution of less than 10 ps. Simulation results using a reference low noise amplifier as a CUT shows the effectiveness of the proposed test method. The tester core has been sent for fabrication in CMOS 0.18-mum technology with a target area of 1 mm2.

The multidimensional logarithmic number system (MDLNS), which has similar properties to the classical logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two, or more, orthogonal bases and has the ability to use multiple MDLNS components, or digits. Unlike the LNS, there is no monotonic relationship between standard binary representations and MDLNS representations. Using look-up tables (LUTs) to perform the mapping function can be unrealistic for hardware implementations when large binary ranges or multiple digits are used. This work proposes a novel range-addressable technique for using look-up tables that allows efficient conversion from binary-to-single or multidigit MDLNS with varying accuracies, depending on the selected implementation.

A new mixed-signal feed-forward neural network for pattern/shape recognition problems is proposed. The network has a mixed-signal structure, operations are performed in analog and weights are stored in digital. To increase the network robustness, on-chip training with Madaline Rule III is used. The proposed architecture uses time-multiplexing to increase the network density and resistive-type neurons for their self-scaling property. The results of an XOR network are presented to test the network.

The multi-dimensional logarithmic number system (MDLNS), with similar properties to the logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two orthogonal bases and the ability to use multiple digits. Unlike the LNS, there is no direct functional relationship between binary/floating point representation and the MDLNS representation. Traditionally look-up tables (LUTs) were used to move from the binary domain to the MDLNS domain. This method can be unrealistic for hardware implementation when large binary ranges or multiple digits are used. This paper introduces a range addressable technique for table look-up arrays that allows efficient conversion from binary to single or multi-digit MDLNS.

A recently introduced double-base number representation has proved to be successful in improving the performance of several algorithms in cryptography and digital signal processing. The index-calculus version of this number system can be regarded as a two-dimensional extension of the classical logarithmic number system. This paper builds on previous special results by generalizing the number system both in multiple dimensions (multiple bases) and by the use of multiple digits. Adopting both generalizations the paper shows that large reductions in hardware complexity are achievable compared to an equivalent precision logarithmic number system.

A new algorithm based on Genetic Programming (GP) for the problem of optimization of Multiple Constant Multiplication (MCM) by Common Subexpression Elimination (CSE) is developed. This method is used for hardware optimization of DSP systems. A solution based on GP is shown in this paper. The performance of the technique is demonstrated in one- and multi-dimensional digital filters with constant coefficients.

The design of a microelectromechanical (MEMS) device that forms part of a micro acousto-magnetic transducer for use with a hearing instrument is described in this paper. A MEMS realization of a microelectromagnetic actuator is used to generate a magnetic field that exerts a force on a permanent micromagnet that has been implanted on the round window of the cochlea. The motion of the implanted magnet will develop traveling waves on the basilar membrane inside the cochlea to give a hearing capability. A modular realization of the micro electromagnet has been proposed that offers the advantage that the magnet's magnetomotive force performance characteristics can be easily changed by depositing additional layers of the modular realization for the magnet core segments and their associated section of excitation winding. The MEMS structures have been designed and simulated using the IntelliSuite MEMS software package from the IntelliSense Corporation.

In this paper, we propose new algorithms for multiple modular exponentiation operations. The major aim of these algorithms is to speed up the performance of some cryptographic protocols based on multiexponentiation. Our new algorithms are based on binary-like complex arithmetic, introduced by K. Pekmestzi (1989) and generalized in this paper.

In this paper, we analyze some of the main properties of a double base number system, using bases 2 and 3; in particular, we emphasize the sparseness of the representation. A simple geometric interpretation allows an efficient implementation of the basic arithmetic operations and we introduce an index calculus for logarithmic-like arithmetic with considerable hardware reductions in lookup table size. We discuss the application of this number system in the area of digital signal processing; we illustrate the discussion with examples of finite impulse response filtering.

This paper describes techniques for using locally connected analog cellular neural networks (CNNs) to implement digital arithmetic arrays; the arithmetic is implemented using a recently disclosed Double-Base Number System (DBNS). The CNN arrays are targeted for low power low-noise DSP applications where lower slew rate during transitions is a potential advantage. Specifically, we demonstrate that a CNN array, using a simple nonlinear feedback template, with hysteresis, can perform arbitrary length arithmetic with good performance in terms of stability and robustness. The principles presented in this paper can also be used to implement arithmetic in other number systems such as the binary number system.

In this paper we introduce an algebraic integer encoding scheme for the basis matrix elements of 8/spl times/8 DCTs and IDCTs. In particular, we encode the function cos(/spl pi//16) and generate the other matrix elements using standard trigonometric identities. This encoding technique eliminates the requirement to approximate the matrix elements; rather we use algebraic 'placeholders' for them. Using this encoding scheme we are able to produce a multiplication free implementation of the Feig-Winograd algorithm.

Presents a rigorous theoretical analysis of the main properties of a double-base number system, using bases 2 and 3. In particular, we emphasize the sparseness of the representation. A simple geometric interpretation allows an efficient implementation of the basic arithmetic operations, and we introduce an index calculus for logarithmic-like arithmetic with considerable hardware reductions in look-up table size. Two potential areas of applications are discussed: applications in digital signal processing for computation of inner products and in cryptography for computation of modular exponentiations.

In this paper, we propose new algorithms for multiple modular exponentiation operations. The major aim of these algorithms is to speed up the performance of some cryptographic protocols based on multi-exponentiation. The algorithms proposed are based on binary-like complex arithmetic, introduced by K. Pekmestzi (1989) and generalized in this paper.

We describe the design and VLSI implementation of a unified synapse-neuron architecture for multi-layer neural networks. A new hybrid building block proposed for this purpose is formed by integrating a partial S-shape neural nonlinearity within a Multiplying DAC synapse. MDAC synapse contains modifications to simplify sign-bit circuit. Small analog circuits generate a distributed S-shape neural function by combining quadratic characteristics of four MOS transistors. The proposed modular neural network architecture features design simplicity and scalability, area efficiency, reduced interconnection problem, improved robustness and digital programmability. Based on the proposed scheme, we have considerably increased the synaptic density in the improved version of a programmable optically-coupled neural network.

This paper explores an architecture for parallel independent computations of inner products over the direct product ring /spl Rfr//sub 257/spl times/17/. The structure is based on the polynomial mapping of the Modulus Replication RNS for calculations over dynamic ranges much larger than the product of the computational moduli. We show that the computational ring is optimal for our purposes, and introduce basic cells for the efficient calculation of all elements of the polynomial ring computations.

In this paper, a new design technique for column-compression (CC) multipliers is presented. Constraints for column compression with full and half adders are analyzed and, under these constraints, considerable flexibility for implementation of the CC multiplier, including the allocation of adders, and choosing the length of the final fast adder, is exploited. Using the example of an 8/spl times/8 bit CC multiplier, we show that architectures obtained from this new design technique are more area efficient, and have shorter interconnections than the classical Dadda CC multiplier. We finally show that our new technique is also suitable for the design of twos complement multipliers.>

We derive a new recursive algorithm for the discrete sine transform (DST) which possesses a very regular structure. The multiplication coefficients in our algorithm can be generated by a simple recursion without the requirement for trigonometric functions; also, no shifts of data are required. In comparison, the existing recursive algorithm for the DST proposed by Wang (1990) has an irregular structure and requires considerable data shifts.>

In order to improve the area and speed of the design of carry lookahead adders (CLAs) using enhanced multiple output domino logic (EMODL), we investigate the trade-off between the number of cascaded gate stages and the gate fan-in of each stage by varying these factors in four different architectural structures for a 32-bit CLA implemented in 1.2 micron CMOS technology. HSPICE simulation results show that the number of cascaded stages is a more critical factor than the gate fan-in.>

This paper discusses new techniques for obtaining high clock rates with complex n-blocks in True-Single-Phase dynamic latch structures. In this paper we present new dynamic current steering latch structures, and apply them to both CMOS and BiCMOS technologies. In the latter case, we exploit the superior properties of the available bipolar devices to achieve substantial speed increases. The latching technique allows complex n-FET blocks (fan-in between 10 and 20) to be used with the TSPC latch at high data rates (over 150 MHz for a 1.2 /spl mu/ CMOS process). The n-FET block is built as a minimized binary tree, which we have termed a switching tree, and interpreted as a general look-up table for use in a variety of bit-level systolic array processors.>

The authors first demonstrate that the forward and inverse discrete cosine transform (DCT, IDCT) can be represented by Chebyshev polynomials of the third and second kind, respectively. Then, they derive recursive algorithms for the DCT and IDCT with arbitrary length from the recursive formulae for the Chebyshev polynomials. The proposed algorithms are particularly suitable for VLSI implementation using array processing architectures.>

Introduces a new recursive algorithm for solving highly ill-conditioned linear algebraic equations without any cutoff error. It has the following properties: (1) all arithmetic operations are just related to integer additions, abstractions, multiplications, and divisions that can be precisely completed without any remainder; (2) the results of every recursion could be verified automatically by the algorithm itself, and (3) the total arithmetic operations are comparable with those of other direct methods. This algorithm is specially suitable for solving the highly ill-conditioned equations; it can also be used in digital signal processing and other related areas.>

A finite polynomial ring structure for mapping inner product computations to parallel independent ring computations over 3-b moduli has been introduced by N.M. Wigley et al. (1992). The main algorithmic computation architecture can be implemented using well-established systolic array mapping principles, and a project to construct a Polynomial Ring Engine (PRE) is underway to exploit the VLSI implementation properties of such computations. A semi-systolic architecture for the input and output conversion mappings that are required in the engine is introduced here. It is shown that the entire mappings procedure can be carried out with pipelined six-input logic blocks and small, fast, binary adders. CMOS implementation techniques for the pipelined blocks are discussed, and the design procedure is illustrated with results from a recently completed module generator.>

The authors describe mapping, scaling, and conversion processes using a new mapping strategy for the modulus replication residue number system (MRRNS). The strategy allows direct mapping of bits of either a purely real or multiplexed bit coded complex number to a set of independent rings, defined by moduli 3, 5, and 7. The MRRNS technique is superior to a large QRNS system operating with a computational dynamic range of over 27 b. A classical radix-4 implementation of a 1024 FFT is used for the comparison. The scaling and conversion procedure is shown to be a set of finite ring calculations followed by an array of ordinary binary adders. The VLSI implementation of the most complex finite ring circuit required (a Mod 7 multiplier) is shown to be easily implemented using the switching tree approach, and mask extracted simulations at 50 MHz demonstrate the embedding of the switching trees in a dynamic pipeline/evaluate circuit with restoring latch.>

The implementation of large input digital neurons using designs based on parallel counters is described. The implementation of the design uses a two-cell library, in which each cell is implemented using switching trees which are pipelined binary trees of n-channel transistors. Results obtained from initial switching trees realized with a 3- mu m CMOS process indicate that the design is capable of being pipelined at 40 MHz sample rates, with better performance expected for more advanced technologies. It appears feasible to develop a wafer-scale implementation with 2000 neurons (each with 1000 inputs) that would perform 3*10/sup 12/ additions/s.>

A modular architecture for very fast digital signal processing (DSP) elements are presented. The computation is performed over finite rings (or fields) and is able to emulate processing over the integer ring using residue number systems. The computations are restricted to closed operations (ring or field binary operators) with the ability to perform limited scaling operations. Computations naturally defined over finite mathematical systems are also easily implemented using this approach. The technique evolves from the decomposition of each closed calculation using the ring/field associativity property. Linear systolic arrays, formed with multiple elements, each of a single generic form, are used for all calculations. The pipeline cycle is determined from the generic cell and is predicted to be very fast by a critical path analysis. The cells are matched to the VLSI medium, and the resulting array structures are very dense. Examples of DSP applications are given to illustrate the technique, and example cell and array VLSI layouts are presented for a 3- mu m CMOS process.>

Very recently, the Quadratic Residue System (QRNS) has been introduced [3,4,5]. Using the QRNS complex multiplication can be performed with two base field multiplication and zero additions. The primary restriction is the limited form of the moduli set for RNS operations. The QRNS has since been geralized for any type of moduli set with an increase in multiplication from 2 to 3 and the resulting number system has been termed Modified Quadratic Residue Number System (MQRNS) [1,2]. In [9] a recursive FIR filter has been developed using the Complex Number Theoretic z-transform (CNT z-transform). Recently, in [6], the implementation of this recursive FIR filter structure has been presented using the QRNS and the MQRNS. Extension of this implementation to generalized FIR filter (Lagrange) has also been briefly presented in [6]. In this paper, we consolidate the implementation aspects of the generalized FIR filter using the MQRNS and also prove that the QRNS is not a suitable medium for the implementation.

Recently, the Quadratic Residue Number System (QRNS)[3,4] and Modified Quadratic Residue Number System (MQRNS)[1,2] have been introduced to perform complex multiplications efficiently. The growing number of complex digital signal processing applications will be implemented more efficiently and economically by using Very Large Scale Integration (VLSI) technology. In this paper we discuss VLSI implementation of complex multiplication using the QRNS and MQRNS. We also concentrate on the aspects of VLSI implementation of Finite Impulse Response (FIR) filter architectures.

The Residue Number System (RNS), its concept, computational power, and applications have been investigated in the past [1,6,7]. Most of the studies have resulted in realizations suitable for discrete implementation [2,8]. This paper introduces a linear systolic array architecture for an RNS based FIR filter suitable for VLSI fabrication. The array, which is completely pipelined, consists of modular cells which only communicate to their nearest neighbor. The connected cells constitute a linear systolic array, and the construction of the cell is such that it can be programmed to function in many different DSP tasks. The final result is the construction of a linear systolic ROM that effectively replaces the previously used discrete ROM arrays.

The Discrete Fourier Transform (DFT) has been adopted in a wide spectrum of Digital Signal Processing (DSP) applications due to the advances in VLSI technology, One dimensional systolic arrays are employed to implement the DFT algorithms where N DFT points can be computed in O(N) time using O(N) area. Residue Number System (RNS) is used to achieve parallelism on the mathematical level, as the arithmetic operations are performed independently for each modulus. Modularity has been realized on both functional and layout levels. Two types of arrays are described. The first array offers higher speed performance, while the second requires less area and is more general. The proposed structures are based on bit parallel processing and lend themselves to pipelining.

Very recently, the Quadratic Residue Number System (QRNS) has been introduced [4,5]. The QRNS is obtained from a mapping of Gaussian integers over a finite ring to a ring of conjugate elements. The conjugate ring has the remarkable property that both addition and multiplication are performed component-wise, therefore complex multiplication only requires two base field multiplications and zero additions. The operations are performed over sub-rings, isomorphic to the conjugate ring via the Chinese Remainder Theorem isomorphism. The primary restriction is the limited form of the moduli set for RNS computations. The QRNS has since been generalized for any type of moduli set with an increase in multiplications from 2 to 3 and the resulting number system has been termed the Modified Quadratic Residue Number System (MQRNS) [1,2]. The direct FIR filter architecture and bit-slice architecture for FIR and recursive digital filters have, been presented using the QRNS and MQRNS [4]. In this paper, the computation of the Complex Number Theoretic Transform(CNTT) and the hardware implementation of a radix-2 butterfly structure, using high-density ROM arrays, are presented. This paper shows that both theQRNS and MQRNS require almost the same amount of hardware for the implementation of the butterfly structure. The computation of Cyclic Convolution in both the QRNS and MQRNS is also discussed.

This paper discusses the use of the Complex Number Theoretic z-transform in implementing a recursive FIR filter structure for frequency samples spaced around the unit circle in the complex number theoretic z-domain. The complex arithmetic operations have been implemented using the Quadratic Residue Number System (QRNS) and Modified Quadratic Residue Number System (MQRNS) for uniformly spaced frequency samples around the unit circle. We discuss the extension of this technique to non-uniformly spaced samples around the unit circle and the resulting filter structure has been termed the generalized number theoretic FIR filter structure. We demonstrate that the MQRNS is the only suitable tool in implementing this recursive FIR filter structure for non-uniformly spaced frequency samples.

The coupling of Residue Number System (RNS) with the recent advances in VLSI technology leads to an efficient implementation of many digital signal processing algorithms. This paper discusses modularity in implementing RNS systems, as modularity is considered an important criterion for VLSI design. An NTT/FFT computational unit is implemented using two multi-look-up table modules as building block units. The layout can be optimized using a look-up table layout procedure which supports the custom design approach. The modularity has been achieved on both functional and layout levels where the interconnection area is minimum.

The implementation of Residue Number System (RNS) architectures using the VLSI technology is discussed. An example of implementing an RNS adder is presented in this paper. Two approaches; the look-up table and the binary adder, have been analyzed in the scope of VLSI criteria where the performance measures are area and time. Two models have been developed, they are flexible, support any modulus, and they provide custom design capabilities. Within the context of this paper, it has been found that the look-up table approach is superior in both area and time up to 5 bits, while the binary adder approach offers better performance for larger moduli.

A real time general purpose signal processor architecture has been developed previously [1,2]. This architecture utilizes parallel, pipeline and distributed processing approaches to achieve high speed computation. Software techniques for programming the data flow signal processor are presented since conventional programming languages are not suitable for programming fast parallel machines. Data flow graphs (DFG) are used to develop an interactive programming environment which will shield the programmer from the internal structure of the data flow signal processor (DFSP). The programming of the DFSP is demonstrated with an image processing application. This example illustrates that the direct convolution can be used to perform computations at video rates.

Recently, the Quadratic Residue Number System (QRNS) has been introduced [4,5,6], which allows the multiplication of complex integers with two real multiplications. Restrictions on the form of the moduli can be removed if an increase in real multiplications from two to three can be tolerated; the resulting number system has been termed the Modified Quadratic Residue Number System (MQRNS). In this paper the MQRNS is defined, and residue to binary conversion techniques in both the QRNS and MQRNS are presented. Hardware implementations of non-recursive and recursive digital filters are also presented where the QRNS and MQRNS structures are realized using a bit-slice architectures.

A design of real time general purpose signal processor architecture is proposed in this paper. The processor is based upon a binary tree structure utilizing multiprocessing, pipeline and distributed processing techniques. A host computer distributes the individual tasks to each processor to perform parallel operations. The residue number system is used for carry free arithmetic operations stored in RAM's and to achieve smaller packet size, eliminating serial transmission of packets as proposed in other data flow machines. The processor is programmable and capable or performing real time signal processing operations.

This paper discusses the implementation of RNS arithmetic modules using VLSI technology. The modules are based on the interconnection of read-only memory look-up tables. The paper first outlines a memory model for a single look-up table which allows the selection of the most efficient layout for memories which do not have power of 2 dimensions. The paper then discusses various examples of interconnected memory modules with associated optimizing layout algorithms. Finally, an example is given of the application of one of the modules to a large prime modulus multiplier.

This paper describes the theory, simulation, and construction of a two-dimensional number theoretic transform (NTT) convolver. The convolver performs indirect convolution by using the cyclic convolution property of a class of generalized discrete Fourier transforms (DFT's) defined over rings isomorphic to direct sums of Galois fields. The paper first presents the theoretical development of the computational element required for computing the generalized discrete Fourier transform (GDFIT) and its inverse. The theory extends the use of base fields to second degree extension fields and provides efficient choices for transform parameters to minimize hardware. The paper next presents results of recent work in multidimensional transform memory structures, and extends this work to the complete convolution process. The two theories are then "married" to produce efficient, very high speed convolution architectures. Simulation results are presented for a second degree extension field image convolver and constructional details are presented for a fast image convolver using 2 base fields and designed to operate as a peripheral to a fast 32 bit minicomputer.

This paper describes the design of an image convolver suitable for the convolution of a (256 × 256) image with large filter impulse responses in under 1/30 of a second. The memory architecture of the convolver is based on the structures associated with parallel and pipelined FFT/NTT processors that use ROM oriented implementation of the Residue Number System and a 2 D radix-r Ordered-input, Ordered-output FFT algorithm. The 2 D convolution operation is performed by the use of overlap-save technique of sectioned convolutions.

The paper describes the design of a high speed two-dimensional digital convolver for use as a preprocessor element in a quality control inspection system. The preprocessor architecture is based on the concepts and structures associates with parallel finite field transforms that have been implemented with read-only-memory arrays. The transform is computed over two second-degree extension Galois Fields to achieve a dynamic range for the multidimensional convolver that is in excess of sixteen bits. A dedicated memory structure that can support a multiplexed 2D NTT butterfly is described. Image processing results obtained by simulating the finite field processor are presented.

This paper describes the construction of a digital signal convolver. The convolution is performed using a Number Theoretic Transform computed over a ring which is isomorphic to three extension fields of second degree:R \simeq GF(191^{2}) \oplus GF(193^{2}) \oplus GF(449^{2}). The transform is implemented using arrays of latched read-only-memories to provide a high throughput computational element. Special procedures are used to reduce ROM size by making use of indices and sub-modular addition techniques. Memory structures are described that allow two records to be convolved at the same time.

This paper considers the implementation of a fast Fourier transform (FFT) structure using arrays of read-only memories. The arithmetic operations are based entirely on the residue number system. The most important aspect of the structure relates to the scaling arrays, which are required to prevent overflow. Because of the limitations of the number system, scaling factors have to be chosen on an a priori basis. This paper develops optimum procedures for choosing both scaling factors and the position of scaling arrays in the structure. Some examples are presented relating to the filtering of speech via a convolutional filter structure.

The residue number system offers parallel processing, digital hardware, implementations for the binary operations of addition, subtraction and multiplication. This paper discusses the use of the residue number system in implementing digital signal processing functions, in which these binary operations abound. The paper covers implementations using arrays of read only memories, and briefly discusses the use of parallel microprocessor structures. ROM array implementations of scaling operations are also presented.

This paper considers an implementation of the FFT based upon the residue number system. This system offers the advantages of using integer based arithmetic operations and a simple hardware realization involving table look-up arrays. The proposed architecture is such that rapid evolutionary changes in read-only-memory technology can be easily incorporated into the hardware realization. In this paper, a generalized expression for predicting RMS relative error that includes A/D quantization, integer normalization and scaling rounding considerations, has been derived. This analysis leads to the optimal choice of several parameters, which are related to error minimization and simplification of the hardware realization. The generalized expression derived with respect to the FFT can also be used to predict errors in high-speed convolution filters.

Haralick has shown that the discrete cosine transform of N points can be computed more rapidly by taking two N-point fast Fourier transforms (FFT's) than by taking one 2N-point FFT as Ahmed had proposed. In this correspondence, we show that if Haralick had made use of the fact that the FFT's of real sequences can be computed more rapidly than general FFT's, the result would have been reversed. A modified algorithm is also presented.