This article presents a microcontroller unit (MCU) based simplified discrete wavelet transform (Sim-DWT) algorithm that can detect high-voltage spindles (HVSs) in local field potential (LFP) signals. The Sim-DWT algorithm operates in an 8-bit MCU, 8MHz operating clock and 16 sample points of buffers to detect HVSs with a frequency range of 5−15Hz. The requirement of only sixteen 8-bit sample points as the window length for calculation and no need for a multiplier render the Sim-DWT easy to implement in an MCU with limited hardware resources. The Sim-DWT is applied in an 8-bit MCU with 6mW power consumption (including IO ports) and was tested for detecting LFP signals in vivo. The design methods and the accuracy of three typical types of mother wavelet functions (Haar, DB4, Morlet) in the Sim-DWT were also tested and compared with those of a PC-based system. The experimental results showed that with appropriately designed cMW functions in the Sim-DWT, HVSs could be detected more accurately than they could be in PC-based software. The present study indicates that the optimized HVS detector (Sim-DWT) can be implemented in an 8-bit MCU with limited hardware resources and is suitable to serve as the digital core in a closed-loop deep brain stimulator microsystem in the future.

An embedded system capable of fusing sensory data is demanded for many portable or implantable microsystems. The continuous restricted Boltzmann machine (CRBM) is a probabilistic neural network not only capable of classifying data reliably but also amenable to very-large-scale-integration (VLSI) implementation. Although the embedded system based on the CRBM has been demonstrated with analog VLSI, the precision required by the learning algorithm is hardly achievable with analog circuits. Therefore, this paper investigates the feasibility of realizing the CRBM as a digital embedded system for fusing the sensory data of an electronic nose (eNose). The fusion here refers to data clustering and dimensional reduction that facilitates reliable classification. The capability of the CRBM to model different types of eNose data is first examined by MATLAB simulation. Afterward, the CRBM algorithm is customdesigned as a digital embedded system within an eNose microsystem. The functionality of the embedded CRBM system is then tested and discussed. With on-chip learning ability, the CRBM-embedded eNose is able to adapt its parameters in response to new data inputs or environmental changes.

The non-isolated buck topology for LED driver is proposed to reduce volume and cost without the need of large transformer. Besides, in the entire universal range of AC input voltage, the proposed self-adjusted feed-forward control (SAFFC) technique ensures small variation in the LED current. The auto-tracking off-time control (ATOTC) technique is also adopted to adjust the off time to guarantee the current accuracy is better than that of the peak current control (PCC) technique while and the efficiency is better than that of the hysteresis current control (HCC) technique. Test chip fabricated in VIS 0.5μm 700V ultra-high voltage (UHV) process demonstrates power factor higher than 0.97, averaged 95% high accuracy, and 95% high efficiency.

A wireless recording system for monitoring the different depth of brain is proposed. The 16-channel recording system includes low-noise amplifiers, analog multiplexers, analog to digital converters, Bluetooth module and an information hub. Neural signals are time-division multiplexed and sampled by an on-board 8-bit analog to digital converter at up to 12k sample/s per channel and overall voltage gain is 5000 V/V. Each channel is controlled by a GUI to fit different kinds of neural signals, which can be observed independently in a PC. We have demonstrated that the board could provide a useful measurement of a rat's neural signals in vivo. The recorded signals can be further processed by the fast Fourier transform to analyze the recorded neural signal activity.

Biological neurons seem able to compute with noise reliably, or even to use noise to achieve probabilistic inference. This paper introduces two neuro-inspired algorithms and their implementation in the Very Large Scale Integration (VLSI). By generalising data variability with noise, the algorithms are able to classify noisy data more reliably. The VLSI implementation further demonstrates the feasibility of utilising electronic noise for stochastic computation. To exploit the intrinsic noise of transistors for computation, two transistors with enhanced and adaptable noise are further developed and modelled. These technologies would allow us to compute with noisy devices just like how the brain computes with noisy neurons.

This paper presents a conductance-based neuronal network in VLSI suitable for studying the caudal photoreceptor (CPR) neuron circuits in the crayfish. By the nullcline approach, the neuron circuit with type-I excitability is designed. The synapse circuit further shares the same schematics with the circuit of ion currents to reduce the design complexity. A full chip containing one CPR neuron, one hair neuron, one inter-neuron, and six synapses is designed with the standard 0.18μm CMOS technology. An analog memory array is also included to store the parameters of the system. By interconnecting two chips to form a complete CPR network of the crayfish, the ability to regenerate a variety of spiking patterns observed in the biological CPR network is examined and discussed.

The Diffusion Network (DN) is a probabilistic model capable of recognising continuous-time, continuous-valued biomedical data. As the stochastic process of the DN is described by stochastic differential equations, realising the DN with analogue circuits is important to facilitate real-time simulation of a large network. This paper presents the translation of the DN into analogue Very Large Scale Integration (VLSI). With extensive simulation, the dynamic ranges of parameters and their representation in VLSI are identified. The VLSI circuits realising the stochastic unit of the DN are further designed and interconnected to form a stochastic system using noise to induce stochastic dynamics in VLSI. The circuit simulation demonstrate that the VLSI translation of the DN is satisfactory and the DN system is capable of using noise-induced stochastic dynamics to regenerate various types of continuous-time sequences.

This paper proposes a low-power, high-resolution Winner-Take-All (WTA) circuit basing on transistors in subthreshold operation. The WTA adapts a tree structure to reduce the effect of process variations. In addition to the traditional way of using positive feedback to improve the comparison performance, we propose to use translinear loop to amplify the difference between two inputs before comparison to achieve high resolution. The circuit has been fabricated with TSMC 0.35μm 2P4M process. The WTA operates with input current as low as a few nano amperes and resolution as high as 0.1%. Measurement results show that the circuit has a non-negligible offset. Discussions on the source of the offset with a proposed solution are also given.

The Diffusion Network(DN) is a stochastic recurrent network which has been shown capable of modeling the distributions of continuous-valued, continuous-time paths. However, the dynamics of the DN are governed by stochastic differential equations, making the DN unfavourable for simulation in a digital computer. This paper presents the implementation of the DN in analogue Very Large Scale Integration, enabling the DN to be simulated in real time. Moreover, the log-domain representation is applied to the DN, allowing the supply voltage and thus the power consumption to be reduced without limiting the dynamic ranges for diffusion processes. A VLSI chip containing a DN with two stochastic units has been designed and fabricated. The design of component circuits will be described, so will the simulation of the full system be presented. The simulation results demonstrate that the DN in VLSI is able to regenerate various types of continuous paths in real-time.

Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.

Real-time recognition of multichannel, continuous-time physiological signals has been crucial for the development of implantable biomedical devices. This work investigates the feasibility of using the diffusion network, a stochastic recurrent neural network, to recognise continuous-time biomedical signals. In addition, a hardware-friendly approach for achieving real-time recognition is proposed and tested with both artificial and real biomedical data. Based on this approach, the diffusion network is demonstrated to exhibit great tolerance against noise and drifts in continuous-time signals being classified.

The continuous restricted Boltzmann machine (CRBM) has been attractive as a probabilistic model both useful in biomedical applications and hardware-amenable. To implement a large-scale CRBM system for real applications, the performance of the CRBM under hardware constraints must be investigated. This paper examines the effects of parameter precision on the performance of the CRBM, identifies the required precision for modelling real biomedical data, and finally proposes a scalable and programmable architecture based on which a CRBM-embedded intelligent system can be formed

This paper presents the VLSI implementation of the continuous restricted Boltzmann machine (CRBM), a probabilistic generative model that is able to model continuous-valued data with a simple and hardware-amenable training algorithm. The full CRBM system consists of stochastic neurons whose continuous-valued probabilistic behavior is mediated by injected noise. Integrating on-chip training circuits, the full CRBM system provides a platform for exploring computation with continuous-valued probabilistic behavior in VLSI. The VLSI CRBM's ability both to model and to regenerate continuous-valued data distributions is examined and limitations on its performance are highlighted and discussed.

We have mapped the contrastive divergence learning scheme of the product of experts (PoE) onto electrical circuits. The issues raised during that hardware translation are discussed in This work and some circuits presenting our solutions are described. The entire learning rule is implemented in mixed-signal VLSI on a 0.6 /spl mu/m CMOS process. Chips results validating our approach and methodology are also presented.

This paper presents VLSI circuits with continuous-valued proba- bilistic behaviour realized by injecting noise into each computing unit(neuron). Interconnecting the noisy neurons forms a Contin- uous Restricted Boltzmann Machine (CRBM), which has shown promising performance in modelling and classifying noisy biomed- ical data. The Minimising-Contrastive-Divergence learning algo- rithm for CRBM is also implemented in mixed-mode VLSI, to adapt the noisy neurons’ parameters on-chip.