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Russell L. Daigle

dblp:56/4064 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 67% Embedded and real-time systems · 33%
Software engineering, system software, and programming languages
2 papers
Operating systems · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
0.021998
Optimizing the Instruction Cache Performance of the Operating System · IEEE Trans. Computers 1998
Optimizing Instruction Cache Performance for Operating System Intensive Workloads · HPCA 1995
Embedded and real-time systems
code layout optimization
0.021998
Optimizing the Instruction Cache Performance of the Operating System · IEEE Trans. Computers 1998
Optimizing Instruction Cache Performance for Operating System Intensive Workloads · HPCA 1995
Memory systems › cache › CPU cache
instruction cache
0.021998
Optimizing the Instruction Cache Performance of the Operating System · IEEE Trans. Computers 1998
Optimizing Instruction Cache Performance for Operating System Intensive Workloads · HPCA 1995

Methods — techniques the papers use, named apart from their topics

locality characterization · 0.0cache interference reduction · 0.0compiler-based code layout optimization · 0.0cache simulation · 0.0
YearPublicationVenuePosition
1998 Optimizing the Instruction Cache Performance of the Operating System
abstract
High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of the basic blocks of the code. However, the performance impact of this technique has been reported for application code only, even though there is evidence that the operating system often uses the cache heavily and with less uniform patterns than applications. It is unknown how well existing optimizations perform for systems code acid whether better optimizations can be found. We address this problem in this paper. This paper characterizes, in detail, the locality patterns of the operating system code and shows that there is substantial locality Unfortunately, caches are not able to extract much of it: Rarely-executed special-case code disrupts spatial locality loops with few iterations that call routines make loop locality hard to exploit, and plenty of loop-less code hampers temporal locality. Based on our observations, we propose an algorithm to expose these localities and reduce interference in the cache. For a range of cache sizes, associativities, lines sizes, and organizations, we show that we reduce total instruction miss rates by 31-86 percent, or up to 2.9 absolute points. Using a simple model, this corresponds to execution time reductions of the order of 10-25 percent. In addition, our optimized operating system combines well with optimized and unoptimized applications.
Josep Torrellas, Chun Xia, Russell L. Daigle
IEEE Trans. Computers3
1995 Optimizing Instruction Cache Performance for Operating System Intensive Workloads
abstract
High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to use an optimizing compiler to minimize cache interference via an improved layout of the code. This technique, however, has been applied to application code only, even though there is evidence that the operating system often uses the cache heavily and with less uniform patterns than applications. Therefore, it is unknown how well existing optimizations perform for systems code and whether better optimizations can be found. We address this problem in this paper. This paper characterizes in detail the locality patterns of the operating system code and shows that there is substantial locality. Unfortunately, caches are not able to extract much of it: rarely-executed special-case code disrupts spatial locality, loops with few iterations that call routines make loop locality hard to exploit, and plenty of loop-less code hampers temporal locality. As a result, interference within popular execution paths dominates instruction cache misses. Based on our observations, we propose an algorithm to expose these localities and reduce interference. For a range of cache sizes, associativities, lines sizes, and other organizations we show that we reduce total instruction miss rates by 31-86% (up to 2.9 absolute points). Using a simple model this corresponds to execution time reductions in the order of 12-26%. In addition, our optimized operating system combines well with optimized or unoptimized applications.>
Josep Torrellas, Chun Xia, Russell L. Daigle
HPCA3