A design toolbox based on Matlab-Spectre co-simulation for the automatic design of sub-nanoampere programmable voltage references is proposed. Starting from the MOS devices available in a selected technology, the tool sizes all possible voltage references, for a 3T architecture, minimizing inaccuracy and temperature coefficient, for a given current consumption and power supply rejection. From the best 3T reference, a programmable reference is designed to generate the supply voltage for low power microprocessors with dynamic supply scaling. Our programmable reference achieves a minimum current consumption of 250 pA, with an output voltage range from 0.5 V to 0.95 V. Tested on a 130-nm node, the tool reduces simulator license usage by more than a factor of 1000.

This paper presents a wireless biosensor for in vivo and real-time plant monitoring, with a dedicated remote server, web interface, and cloud data storage. The biosensor is based on a two-wire organic electrochemical transistor nested in the plant stem. When stimulated, the device provides relevant information on the concentration of nutrients in the sap, allowing assessment of the plant health status and early detection of drought stress. The system is based on an ultra-low power circuit interface and a microcontroller with an embedded NbIoT/LTE-M radio. Preliminary results show that the biosensor node can operate under battery for several months, making it suitable for several seasonal crops.

This paper presents a novel write system for memory array with RRAM devices. Our design targets the minimization of the write circuit area and a more compact memory array, by avoiding large-area IO transistors and exploiting the back-gate control in FD-SOI technologies. Indeed, thanks to the Flipped (F)-1T1R cell, replacing the standard 1T1R for the data storage, read and write peripheral circuits, on the columns, can be designed with core devices, to withstand the low reset voltage, for a reduced column pitch. Designed in a 22-nm FD-SOI technology, without IO devices, our write system can safely provide a forming voltage above 3 V and a reset voltage of 1.35 V, with very low values of leakage current. From the optimized layout, we obtained an area ratio, between the write system and the full memory, below 10%, for a memory array with 400 rows and columns.

This paper proposes a dual-output Sample-and-Hold (SH) ultra low-power programmable voltage reference (SH-PVR). Our mixed-signal system regulates the ripple voltage on the output channels due to the leakage current, by monitoring the amplified ripple on a channel replica. The refresh frequency of the references is minimized for the minimum current consumption, while maintaining the ripple specification. Designed and implemented in TSMC 180-nm CMOS technology, the SH-PVR provides two references, with a programmability range [0.5 - 2]$\mathbf{V}$, and a step size of 50 mV. The system achieves a current consumption of 330 nA, with an output ripple below 10$\mu \mathbf{V}$, and it is suitable for ultra low-power devices for IoT, wearable, and implantable applications.

This paper proposes an analytical model for the optimized design of a switched-capacitor programmable voltage reference (SC-PVR). This PVR topology guarantees a straightforward design, easy portability across different technology nodes, and does not require any special technology option. The developed model allows the study of the trade-offs and the a priori evaluation of the system performance. The circuit design optimization is carried out with MATLAB, and it permits SC-PVR to achieve current consumptions of few tens of nanoampere, with a voltage ripple specification of 500 μV. An SC-PVR has been designed in 65-nm CMOS technology, with a sizing extracted by the model optimization. Transistor-level simulation results are aligned with MATLAB results and confirm that the investigated architecture is suitable for ultra low-power applications.

This paper proposes a novel architecture for the generation of a programmable voltage reference: the background-calibrated (BC)-PVR. Our mixed-signal architecture periodically calibrates a static ultra low-power voltage reference generator, from an accurate bandgap reference. The portion of the chip used for the calibration can be powered down with a programmable duty-cycle. The system aims to fully exploit the small temperature derivative vs time$D_{T}$of several application domains to minimize the average current consumption. The BC-PVR has been designed and implemented in TSMC 55-nm CMOS technology, and it achieves the largest reported programming reference output range [0.42 - 2.52] V, over the temperature range [−20, 85] °C. The duty-cycle mode allows nanoampere current consumption, and the large design flexibility permits to optimize the system performance for the specific application. These features make the BC-PVR very well-suited for power-constrained electronic systems.

This paper presents a switched-capacitor Sigma-Delta modulator designed in 90-nm CMOS technology, operating at 1.2-V supply voltage. The modulator targets healthcare and medical diagnostic applications where the readout of small-bandwidth signals is required. The design of the proposed A/D converter was optimized to achieve the minimum power consumption and area. A remarkable performance improvement is obtained through the integration of a low-noise amplifier with modified Miller compensation and rail-to-rail output stage. The manuscript also presents a set of design equations, from the small-signal analysis of the amplifier, for an easy design of the modulator in different technology nodes. The Sigma-Delta converter achieves a measured 96-dB dynamic range, over a 250-Hz signal bandwidth, with an oversampling ratio of 500. The power consumption is$30~\mu \text{W}$, with a silicon area of 0.39 mm2.

This paper describes the design of a temperature sensor in 65-nm CMOS technology, intended for food monitoring in IOT and RFID contexts. The digitally-assisted readout scheme combined with a reduced design complexity in the PNP BJT sensor analog front-end allows the minimization of the power consumption. The full sensor occupies an area of 0.26 mm2, with an inaccuracy of ±0.37oC over the [-20oC÷80oC] temperature range, and a power consumption lower than 15.5 μW with a conversion speed of 30 ms.

In contrast to video sensors which just "watch " the world, present-day research is aimed at developing intelligent devices able to interpret it locally. A number of such devices are available on the market, very powerful on the one hand, but requiring either connection to the power grid, or massive rechargeable batteries on the other. MicrelEye, the wireless video sensor node presented in this paper, targets a different design point: portability and a scanty power budget, while still providing a prominent level of intelligence, namely objects classification. To deal with such a challenging task, we propose and implement a new SVM-like hardware-oriented algorithm called ERSVM. The case study considered in this work is people detection. The obtained results suggest that the present technology allows for the design of simple intelligent video nodes capable of performing local classification tasks.

One prominent disadvantage of SVM when implemented in wireless sensor networks (WSNs) is the run-time complexity of classifier, which linearly increases with the number of support vectors (SVs). This disadvantage prevents applying SVM in some applications. In this paper, we propose an improved reduced set method to find solutions characterized by few number of vectors and having good generalization properties. The idea behind our improved method is to combine finding patterns with maximum absolute margin and performing gradient-descent to find new patterns in new decision function. Our method can partially overcome the non-convexity difficulty. The application context is that of WSNs, where a general sensor node is equipped with fixed point CPU. The performance of fixed point implementation of our algorithm is also provided.

Computations in Support Vector Machines (SVM) involve a large number of vector multiplications. When implementing such architectures on a stand alone, embedded system, the complexity of the hardware implementation of the multipliers can be a limiting factor. This paper proposes a representation of numerical data to be processed by an approximation of the logarithm of the number, thus allowing the substitution of expensive multipliers with simpler adders. Additional circuitry is proposed to translate between standard and the proposed pseudo-logarithmic number representation. The operations for the representation translation, addition and multiplication with pseudo-logarithmic numbers have been implemented in software and several experiments have been carried out to assess their performance when used in a SVM-based computational architecture that was used for data classification. The results obtained show that the proposed representation yields an accuracy that is comparable with that obtained by using standard floating point or fixed point number representation.

This paper presents an accurate time-domain analysis of operational amplifiers' step response. Both slewing and linear settling phases are investigated in order to correct some discrepancies found in previous literature works. Moreover theoretical results are exploited developing a CAD tool for the automatic synthesis of high-gain highspeed operational amplifiers. Transistor level simulations are performed with MOS lev. 2 and BSIM3v3 models for a telescopic OTA evaluated in the design of a 12-b 200-MS/s pipelined analog-to-digital converter in a 0.35-/spl mu/m BiCMOS technology. The excellent agreement between predicted and simulated results are the consequence of an improved analysis of the slewing-to-linear transition.

The paper discusses the design of the analog frontend of a passive UHF RFID tag, compatible with ISO/IEC~18000-6b standard. An efficient ESD-protected power retrieving circuit, based on the antenna features, a rectifier bridge and a charge pump, is introduced, as well as an auto-calibrated clock generator. The chip, implemented in a 0.18μm digital CMOS technology, does not need any post-fabrication trimming or external component besides the antenna; according to simulations, a correct communication is achieved at a distance of several meters between reader and tag.

The availability of powerful field programmable gate arrays (FPGA) has been exploited for their ability to rovide hardware solutions for many application areas, resulting in high-performance systems that can operate in real time by operating in parallel. The support vector machine computational paradigm can be cast as a collection of multiple streams operating in parallel on one such FPGA. This paper presents a parallel architecture that implements an SVM on a Xilinx FPGA. The results obtained by using this architecture for a complex pattern classification from high-energy physics involving thousands of patterns are reported and discussed, comparing the performance obtained by this architectural solution to that of a simpler sequential architecture.

In clearing terrains contaminated or potentially contaminated by landmines and/or unexploded ordnances (UXOs), a quick wide-area surveillance is often required. Nevertheless, the identification of dangerous areas (instead of the detection of each subsurface object) can be enough for some scenarios/applications, allowing a suitable level of security in a cost-saving way. In such a framework, this paper describes a probabilistic approach for the definition of risk maps. Starting from the measurement of the scattered electromagnetic field, the probability of occurrence of dangerous targets in an investigated subsurface area is determined through a suitably defined classifier based on a support vector machine. To assess the effectiveness of the proposed approach and to evaluate its robustness, selected numerical results related to a two-dimensional geometry are presented.

In this paper we show how to map a LSSVM on digital hardware. In particular, we provide a theoretical analysis of quantization effects, due to finite register lengths, that leads to some useful bounds for computing the necessary number of bits for a correct hardware implementation. Then, we describe a new FPGA-based architecture, the KTRON, which implements the feed-forward phase of a LSSVM.

We present in this paper an algorithm for Support Vector Machine (SVM) learning, which can be implemented using fixed-point math. The advantages of the fixed-point representation, respect to the more common floating-point one, allows us to address digital VLSI implementations of SVM. In particular, simple algorithms and simple architectures can be exploited for targeting programmable devices like Field Programmable Gate Arrays (FPGAs), which are the basis of many embedded systems. This paper focuses on the SVM learning algorithm: for the complete version of this work, including an actual FPGA realization.

A new online inverse scattering methodology is proposed. The original problem is recast into a regression estimation and successively solved by means of a support vector machine (SVM). Although the approach can be applied to various inverse scattering applications, it is very suitable for dealing with buried object detection. The application of SVMs to the solution of such problems is firstly illustrated. Then some examples, concerning the localization of a given object from scattered field data acquired at a number of measurement points, are presented. The effectiveness of the SVM method is evaluated in comparison with classical neural network based approaches.

In this paper, we propose a digital architecture for support vector machine (SVM) learning and discuss its implementation on a field programmable gate array (FPGA). We analyze briefly the quantization effects on the performance of the SVM in classification problems to show its robustness, in the feedforward phase, respect to fixed-point math implementations; then, we address the problem of SVM learning. The architecture described here makes use of a new algorithm for SVM learning which is less sensitive to quantization errors respect to the solution appeared so far in the literature. The algorithm is composed of two parts: the first one exploits a recurrent network for finding the parameters of the SVM; the second one uses a bisection process for computing the threshold. The architecture implementing the algorithm is described in detail and mapped on a real current-generation FPGA (Xilinx Virtex II). Its effectiveness is then tested on a channel equalization problem, where real-time performances are of paramount importance.

The recurrent network of Xia et al. (1996) was proposed for solving quadratic programming problems and was recently adapted to support vector machine (SVM) learning by Tan et al. (2000). We show that this formulation contains some unnecessary circuits which, furthermore, can fail to provide the correct value of one of the SVM parameters and suggest how to avoid these drawbacks.

We propose a fast way to perform the gradient computation in Support Vector Machine (SVM) learning, when samples are positioned on an m-dimensional grid. Our method takes advantage of the particular structure of the constrained quadratic programming problem arising in this case. We show how such structure is connected to the properties of block Toeplitz matrices and how they can be used to speed-up the computation of matrix-vector products.

In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.

We propose a VLSI friendly algorithm for the implementation of the learning phase of support vector machines (SVM). Differently from previous methods, that rely on sophisticated constrained nonlinear programming algorithms, our approach finds a simple updating rule that can be easily implemented in digital VLSI.