The decade that we have embarked upon presents enormous challenges for Europe. The 2020 strategy for smart, sustainable and inclusive growth recognises the key role higher education must play if the ambitions for Europe in a fast-changing global reality are to be realised. This implies widening access to lifelong learning to as many European citizens as possible and it is vital that measures are implemented to transform our reality towards this direction. Notably, labour markets increasingly require more graduates with specialized knowledge and competences and substantial investment has to be made in education systems to ensure that this demand is met. The COMPASS project aims to the Composition of Lifelong Learning Opportunity Pathways through Standards-based Services investing on the establishment of a cohesive, strategic partnership for the longterm promotion of LLL-related European strategies and the development of instruments that will raise the awareness of both learning opportunity providers and learning opportunity seekers and stimulate the design of policies for enhancing ET with alternative, flexible pathways on the basis of easy, technology-enhanced access to learning opportunities.

In this work we present a novel module termed rotatable counter and its use to design an on-chip generator of SIC pairs. The presented generator is optimal in time, in the sense that it generates the n-bit SIC pairs in time n × 2^n clock cycles, i.e. equal to the theoretical minimum.

Symmetric Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing while at the same time skipping the signature prediction phase required in transparent BIST schemes, achieving considerable reduction in test time. In this work the utilization of accumulator modules comprising adders implementing binary addition is proposed.

The application of single input change (SIC) pairs of test patterns is very efficient for sequential, i.e. stuck-open and delay fault testing. In this paper a novel implementation for the application of SIC pairs is presented and a formal proof of its completeness is provided. The presented generator is optimal in time, in the sense that it generates the n-bit SIC pairs in time n × 2n, i.e. equal to the theoretical minimum. Comparisons with the schemes that have been proposed in the open literature that generate SIC pairs in optimal time, reveal that the proposed scheme requires less hardware overhead.

In this work we present a new scheme for the on-chip application of test patterns utilizing an accumulator structure whose inputs are driven by a barrel shifter. The consecutive patterns applied to the inputs of the Circuit Under Test differ in one bit, therefore the power consumed is lower compared to previously proposed accumulator-based pattern application schemes.

In this work, we combine the input vector monitoring concurrent BIST paradigm with input reduction (in order to reduce the Concurrent Test Latency) and Space Compaction of the output responses (in order to reduce the hardware overhead) and examine its implementation on the concurrent testing of sequential modules.

One of the well-known problems in response verification is aliasing, i.e., the event that a series of responses containing errors results in a signature equal to that of the error-free response sequence. In this paper, we propose a scheme to reduce aliasing in accumulator-based response verification. The proposed scheme is based on monitoring the value of the carry output of the accumulator. Experimental study indicates that the proposed scheme achieves significantly less hardware overhead for the same reduction in the aliasing probability than previously proposed schemes.

Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the circuit without imposing a need to set the circuit offline to perform the test. These schemes are evaluated based on the hardware overhead and the concurrent test latency (CTL), i.e., the time required for the test to complete, whereas the circuit operates normally. In this brief, we present a novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM-like structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the proposed scheme is shown to perform significantly better than previously proposed schemes with respect to the hardware overhead and CTL tradeoff.

Input vector monitoring concurrent BIST schemes perform testing concurrently with the operation of the circuit. In this work a novel input vector monitoring concurrent BIST scheme is presented that compares favorably to previously proposed schemes with respect to the required hardware overhead.

Input Vector Monitoring Concurrent Built-In Self Test (BIST) schemes provide the capability to perform testing while the Circuit Under Test (CUT) operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. In this paper a novel input vector monitoring concurrent BIST scheme is presented, that reduces considerably the imposed hardware overhead compared to previously proposed schemes.

Weighted pseudorandom built-in self test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generation, since they result in both low testing time and low consumed power. In this paper an accumulator-based 3-weight test pattern generation scheme is presented; the proposed scheme generates set of patterns with weights 0, 0.5, and 1. Since accumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down the hardware of BIST pattern generation, as well. Comparisons with previously presented schemes indicate that the proposed scheme compares favorably with respect to the required hardware.

Input vector monitoring concurrent Built-In Self-Test (BIST) schemes can circumvent problems appearing separately in on-line and off-line BIST techniques. The concurrent test latency of an input vector monitoring concurrent BIST scheme is the time required in order to complete the concurrent test. In this paper a novel input vector monitoring concurrent BIST scheme is presented. The proposed BIST scheme is shown to have lower hardware overhead for the same values of the concurrent test latency compared to previously proposed schemes.

We propose a new scheme for reducing the test application time in accumulator-based test-pattern generation. Within this framework, we reduce the problem of efficiently generating test-patterns to that of finding the shortest Hamiltonian path in an associated directed graph. The resulting scheme exhibits extremely low demand for hardware based on a combination of decoders whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate the superiority of the proposed scheme over the previously-published test-set embedding approaches for accumulator-based test generation.

Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation. In (n,k)-adjacent bit pseudo-exhaustive test sets, all 2kbinary combinations appear to all adjacentk-bit groups of inputs. With recursive pseudoexhaustive generation, all (n,k)-adjacent bit pseudoexhaustive tests are generated fork¿nand more than one modules can be pseudo-exhaustively tested in parallel. In order to detect sequential (e.g., stuck-open) faults that occur into current CMOS circuits, two-pattern tests are exercised. Also, delay testing, commonly used to assure correct circuit operation at clock speed requires two-pattern tests. In this paper a pseudoexhaustive two-pattern generator is presented, that recursively generates all two-pattern (n,k)-adjacent bit pseudoexhaustive tests for allk¿n. To the best of our knowledge, this is the first time in the open literature that the subject of recursive pseudoexhaustive two-pattern testing is being dealt with. A software-based implementation with no hardware overhead is also presented.

Input Vector Monitoring Concurrent Built-In Self Test schemes provide the capability to perform testing while the Circuit Under Test operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. The Concurrent Test Latency of an input vector monitoring scheme is the time required for the concurrent test to complete. Input Vector Monitoring Concurrent BIST schemes that have been proposed to date, are based mainly on test sets containing binary (1 or 0) values. Test sets extracted by modern CAD tools, largely contain don't care (dasiaXpsila) values. In this work a novel input vector monitoring concurrent BIST scheme is presented, based on a test set containing dasiaXpsila values. The proposed scheme compares favourably with respect to the hardware overhead - concurrent test latency trade off with previously proposed techniques.

A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding approaches for accumulator-based test generation.

Testing of word-organized memories has been performed in one of these three ways: (1) by repeatedly applying a test for bit-oriented memories using different data backgrounds (which depend on the used intraword fault model), (2) by applying special tests to target intraword faults in addition to applying tests for bit-organized memories, or (3) by applying march tests bit-by-bit to the memory words. The latter solution results in decreased hardware overhead. In this paper, a novel Built-in Self-Test (BIST) scheme is proposed to serially apply march tests bit-by-bit to word-organized RAMs, utilizing an ALU whose inputs are driven by a barrel shifter. Comparisons with schemes that have been proposed in the open literature for the same purpose reveal that the proposed scheme achieves the same fault coverage within the same or lower time and with lower area overhead. More precisely, an overhead of n + 3 gates is required for the application of the required patterns to the RAM inputs and the evaluation of the corresponding outputs, as opposed to the 8n or 11n gates required by schemes proposed previously.

Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.

Transparent built-in self test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this paper the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. It is shown that in this way the hardware overhead, the complexity of the controller, and the aliasing probability are considerably reduced.

Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional built-in self test (BIST) generators rise the power and energy consumption during testing, boosting the need to add low-power solutions to the arsenal of BIST pattern generators. In this work, the utilization of gray code generators is proposed as a low-power BIST solution; more precisely, we propose an algorithm to embed a test pattern into a sequence generated by a gray code generator. Hence, test sets can be embedded into gray sequences.

Weighted pseudorandom BIST schemes have been efficiently utilized in order to drive down the number of vectors required to achieve complete fault coverage in built in self test (BIST) applications. Sets of patterns comprising weights 0, 0.5 and 1 have been successfully utilized within the weighted pattern generation paradigm. In this paper an accumulator-based scheme is presented, that generates set of patterns with weights 0, 0.5 and 1. Since accumulators and ALUs are commonly found in current VLSI chips, the presented scheme can be efficiently utilized to drive down the hardware of BIST pattern generation.

Manufacturing testing is carried-out once in order to ensure the correct operation of the circuit under test right after fabrication, while either periodic off-line testing or concurrent on-line testing is carried-out in order to ensure that the circuit under test continues to operate correctly in field. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform all types of testing, namely manufacturing, periodic off-line and concurrent on-line. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing. In this paper a novel input-vector monitoring concurrent BIST scheme based on a pre-computed test set is introduced. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both on line and off-line testing

The test set embedding problem is typically formed as follows: Given an n-stage pattern-generator and a test set, calculate the minimum number of steps that the generator needs to operate in order to generate all vectors in the test set. The cornerstone of a test set embedding technique is its embedding algorithm. An embedding algorithm, given an n-stage pattern generator initialized to a starting value and an n-bit target vector V, calculates the location of V in the generated sequence. In this paper, a novel algorithm is presented that calculates the location of a vector into a sequence generated by an n-stage accumulator accumulating a constant pattern. The time complexity of the algorithm is of the order O(n). To the best of our knowledge, this is the first embedding algorithm of the order O(n) that has been presented in the literature. Experiments performed on well-known benchmark circuits reveal that complete test sets are embedded in sequences of practically acceptable length.

Built-in self-test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in online and in offline BIST schemes. An important measure of the quality of an input vector monitoring concurrent BIST scheme is the time required to complete the concurrent test, termed concurrent test latency. In this paper, a new input vector monitoring concurrent BIST technique for combinational circuits is presented which is shown to be significantly more efficient than the input vector monitoring techniques proposed to date with respect to concurrent test latency and hardware overhead trade-off, for low values of the hardware overhead.

Manufacturing test is carried-out once to ensure the correct operation of the circuit under test right after fabrication, while testing is carried-out periodically to ensure that the circuit under test continues to operate correctly on the field. The use of offline built-in self-test (BIST) techniques for periodic testing imposes the interruption of the normal operation of the circuit under test. On the other hand, the use of input vector monitoring concurrent BIST techniques for periodic testing provides the capability to perform the test, while the circuit under test continues to operate normally. In this paper, a novel input-vector monitoring concurrent BIST technique for combinational circuits based on a self-testing RAM, termed R-CBIST, is presented. The presented technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead, and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be utilized to test ROM because it results in small hardware overhead, whereas there is no need to stop the ROM normal operation.

The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns results in favorable results for sequential fault testing. In this paper, a novel algorithm for the generation of SIC pairs is presented, termed Accumulator-based test generation for Robust sequential fault testing in Near-optimal time (ARN). ARN is implemented in hardware utilizing an accumulator whose inputs are driven by a barrel shifter. Since such structures are commonly found in general-purpose or specialized microprocessors or digital signal processors (DSP), the presented architecture provides a practical solution for the built-in testing of such circuits.

In this paper a novel input vector monitoring concurrent BIST technique based on a RAM (R-CBIST) is presented. This technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be used in practice for exhaustive testing of ROMs since it results in small hardware overhead whereas no need to stop the ROM normal operation is required.

Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Among the BIST techniques the Comparative Concurrent BIST (C-BIST) has various advantages since it provides for off-line test generation, when it is desirable, and thus accomplishes a mixed on-line/off-line BIST scheme. However, in C-BIST when the test sequence is long, the time required for all the test vectors to appear among the normal inputs to the circuit (test latency) is significantly long. Modifications of the C-BIST technique have been proposed in order to reduce the test latency. In this paper we propose a new C-BIST technique termed windowed-CBIST (w-CBIST) for test latency reduction. The proposed technique is shown to be significantly more efficient from the previous methods with respect to test latency and hardware overhead.