Bridge faults are caused by permanent circuit failures which result in two signal wires in a logic network becoming accidentally shorted. Such faults cannot be modeled as stuck-at faults. Some of them have the effect of transforming a combinational logic circuit into a sequential circuit.

We propose a novel dynamic fault-tolerance scheme for universal adaptive logic modules. The scheme is based on a proposed reducible decompostion of a switching function.

General methods are presented for analyzing the terminal behavior of the classes of one-dimensional unidirectional iterative systems with arbitrary many intercell leads and two-dimensional iterative systems with unidirectional signal flow and one intercell lead on each axis, where the cell structure is either an arbitrary linear switching circuit (combinational) or an arbitrary linear sequential machine (LSM).

An analysis of the state structure and of the autonomous behavior of iterative systems belonging to the class of one-dimensional unidirectional single-output autonomous iterative arrays with one intercell lead and the cell structure of a linear sequential machine (LSM) is presented. An algorithm is developed for computing the state structure of any such iterative system with the cell structure of a minimal LSM. Another algorithm computes the cycle structure of the output sequences generated by any such iterative system, with the cell structure of an arbitrary single-input single-output LSM.