Minimizing the channel area is essential for achieving high resolution in cortical neurostimulators. This is, however, complicated by on one hand the high impedance of microelectrodes, necessitating bulky high-voltage circuits to deal with the resulting high swing, and on the other hand the requirement for accurate charge balancing, often resulting in large analog circuits. To address these challenges, we present a 256 channel neurostimulator SoC which employs transistor stacking in 65 nm standard CMOS to achieve 10.4 V output swing as well as digital time domain calibration (DTDC) for charge-balanced stimulation. Stimulator variability is mapped on a model capturing the process variability in only 34 bytes per channel, allowing on-chip storage and on-the-fly computation of DTDC corrections. Furthermore, a novel HV shorting switch is included in every channel which allows discharging the electrode. The switch withstands an 11 V output swing in both ON and OFF conditions with an average on resistance of 4k$\Omega $. Including both the HV switch and global DTDC overhead, the effective area per channel is only 0.0206 mm2.

Level shifters are widely used in multi-voltage-domain digital circuits. The requirements of level shifters include: high conversion speed, low power, small transistor count, wide conversion range, and variation tolerance. However, most existing designs can cover only a subset, instead of all, of these requirements. This work proposes a novel Charge-Injection-Positive-Latch (CIPL) level shifter that tackles all problems at once. The design is validated through simulation in a 16nm FinFET technology, with 640ps/130ps conversion speed for 300mV to 800mV voltage conversion, 260mV minimal operating voltage, and 238nW average power. It enables more extreme applications for DVFS on a multi-voltage-domain design.

The demand for high-capacity and energy-efficient memory solutions has surged in the era of data-centric computing, particularly for Artificial Intelligence (AI) and Machine Learning (ML) workloads. This paper introduces a novel memory architecture leveraging Charge-Coupled Device (CCD) technology, engineered in a sequential-access block memory configuration, to enhance Compute-near-Memory (CnM) systems. We propose an optimized 3D IGZO CCD block memory as an on-chip weight buffer for high-capacity CnM systems. Our approach achieves 2.95−131.26× improvement in area efficiency and 1.32−4.33× improvement in energy efficiency compared to SRAM solutions.

In biomedical sensor platforms, low energy consumption is of utmost importance to extend battery life. A dominant contributor in the energy budget of such platforms is the always-on recording memory. Hence, a low energy memory is required. This paper implements such a memory with aggressive voltage scaling to run the memory in the sub-threshold region during retention. Fine grained forward error correction is a key enabler for this. It allows operation of the memory beyond the point of first failure and acts similar to EDAC techniques for timing failure detection in voltage-scaled microcontrollers. The memory is embedded in a RISC-V microcontroller and fabricated in a 22nm FDSOI technology. Measurements show an always-on retention voltage down to 170mV, which results in a total average power of only 5.11uW, a 70% reduction compared to the signoff point. The memory is extensively tested with memtest and found to be fully functional up to 1.2 MHz.

An amplifier placed within a pixel is advantageous, as it offers gain at the first stage in the signal readout chain, but is limited by non-linearity. This paper presents a readout-circuit technique, that addresses the non-linearity issue of a current-mode pixel. The proposed circuit named ‘Pixel Follower’ compensates for the non-linearity by inverting it via feedback implemented locally. This avoids having to reduce the in-pixel amplifier gain, or sending any feedback signal to the pixel itself, thus greatly simplifying the design compared to other published techniques. The circuit has been manufactured in a Low Temperature Polycrystalline Silicon on foil process focusing on all LTPS-TFT large-area imager applications. The circuit operates at 5V supply and draws 200μW power with a total readout interval of 50μs. With a dynamic range of 2V on the pixel photo-diode voltage, the integral non-linearity is measured to be 2% outperforming the current state-of-the-art for large-area imagers.

The impact of variability in CMOS technology increases with scaling and low-voltage operation, where conventional design flows need to manage large design margins to ensure an acceptable yield. In this article, we present a novel methodology to improve the digital circuit’s energy efficiency binomial eliminating the unnecessary margins and guaranteeing the same$4\sigma $production yield. The proposed methodology is based on an automated in situ error prediction strategy fully compatible with a conventional industrial design flow. The main field of application is the design of generic DSP blocks. As such, the methodology is demonstrated on a 22-nm CMOS Viterbi decoder. Results show that with this methodology, we can safely recover more than 95% of the conventional energy design margin, improving the energy efficiency by 30%–40% with a low area overhead of 6%. Fabricated and tested circuits operate with a maximum of 16 mV voltage margin, providing an additional maximum energy benefit of 55% compared to a replica-based adaptive voltage scaling (AVS) system.

This paper is the first to present an implementation of a cryptographic circuit in 28nm FD-SOI using near-threshold design. The implemented cipher, Ketje Jr, is a lightweight authenticated encryption algorithm. The energy consumption of representative authenticated encryption operations as well as the information leakage through the power consumption side-channel are evaluated. The results show that an ultra-low energy implementation can be achieved, and that the near-threshold design has little influence on the Signal to Noise Ratio in the power measurements of our chip.

Analog in memory computing (AiMC) is a promising hardware solution to efficiently perform inference with deep neural networks (DNNs). Similar to digital DNN accelerators, AiMC systems benefit from aggressively quantized DNNs. In addition, AiMC systems also suffer from noise on activations and weights. Training strategies to condition DNNs against weight noise can increase the efficiency of AiMC systems by enabling the use of more compact but more noisy weight memory devices. In this work, we utilize noise-aware training and introduce gradual noise training and network width scaling to increase the tolerance of DNNs against weight noise. Our results show that noise-aware training and gradual noise training drastically lowers the impact of weight noise without changing the network size. By utilizing network width scaling, the weight noise tolerance is increased even more with the penalty of more network parameters.

This work elaborates on an amorphous Indium-Gallium-Zinc Oxide thin-film transistor model for a dual-gate self-aligned transistor configuration, enabling the design and realization of complex integrated circuits. The model originates from a mobility-enhanced transistor behavior model, whereby the additional backgate impacts key parameters, such as threshold voltage, mobility and subthreshold slope. The model has been validated for the full design flow and compared to measurement results, from single transistors, to inverters, ring oscillators and RFID transponder chips.

To compensate for time-zero (due to process variation) and time-dependent (due to e.g. Bias Temperature Instability (BTI)) variability, designers usually add design margins. Due to technology scaling, these variabilities become worse, leading to the need for bigger design margins. Typically, only worst-case scenarios are considered, which will not present the actual workload of the targeted application. Alternatively, mitigation schemes can be used to counteract the variability. This paper presents a run-time design-for-reliability scheme for memory Sense Amplifiers (SAs); SAs are an integral part of any memory system and are very critical for high performance. The proposed scheme mitigates the impact of time-dependent variability due to aging by using an on-line control circuit to create a balanced workload. The simulation results show that the proposed scheme can reduce the most critical figures-of-merit, namely the offset voltage shift and the sensing delay of the SA with up to ~40% and ~10%, respectively, depending on the stress conditions (temperature, voltage, workload).

Several applications in machine learning and machine-to-human interactions tolerate small deviations in their computations. Digital systems can exploit this fault-tolerance to increase their energy-efficiency, which is crucial in embedded applications. Hence, this paper introduces a new means of Approximate Computing: Dynamic-Voltage-Accuracy-Frequency-Scaling (DVAFS), a circuit-level technique enabling a dynamic trade-off of energy versus computational accuracy that outperforms other Approximate Computing techniques. The usage and applicability of DVAFS is illustrated in the context of Deep Neural Networks, the current state-of-the-art in advanced recognition. These networks are typically executed on CPU's or GPU's due to their high computational complexity, making their deployment on battery-constrained platforms only possible through wireless connections with the cloud. This work shows how deep learning can be brought to IoT devices by running every layer of the network at its optimal computational accuracy. Finally, we demonstrate a DVAFS processor for Convolutional Neural Networks, achieving efficiencies of multiple TOPS/W.

Massive MIMO has the potential to bring great spectral and energy efficiency improvements, making it a very promising technology for future wireless systems. Essential to achieve the gains in practice, is the ability to realize the many antenna paths at low complexity. In this paper, we consider the potential of processing at the semiconductor edge by allowing voltage over-scaling and complete antenna signal failures, focusing on the per-antenna digital functionality that dominant the DSP complexity. The impact of the resulting hardware errors on the performance of Massive MIMO transmission is analyzed. It shows that the inherent redundancy in the system brings a solid tolerance to sporadic hardware errors. Potential control tactics are introduced, that could further optimize the operation of the error-prone circuitry. We anticipate that by exploiting the system and circuit margins, up to 40% power reduction could be achieved on the considered DSP functions without sacrificing performance in many traffic scenarios.

Spin-transfer torque magnetoresistance random access memory is a major contender for static random access memory replacement in embedded caches at advanced fin field effect transistor nodes. It suffers, however, from the low resistance difference between the bistable states of the magnetic tunnel junction (MTJ). Variability on MTJ resistance and access transistors makes reliable read-out even more challenging. This triggered the use of complementary cells for low level caches needing high performance. This paper, focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell's three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%. The novel variation resilient write operation also uses all three transistors and takes advantage of the inherent MTJ characteristics and complementary operation of the cell. This increases the write performance by 2× and reduces the write energy by 3× compared with the 2T 2MTJ cell and by 1.5× compared with the 1T 1MTJ cell.

This paper investigates the impact of aging in the read path of 32nm high performance SRAM; it combines the impact on the memory cell, on the sense amplifier, and on the way they interact. The analysis is done while considering different workloads and by inspecting both the bit-line swing (which reflect the degradation of the cell) and the sensing delay (which reflects the degradation of the sense-amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results show that in addition to the sense amplifier degradation, the cell degradation also contributes to the sensing delay increase; the share of this contribution depends on the cell design. Moreover, this sensing delay becomes worst at stressy workloads.

True random number generators are essential components in cryptographic hardware. In this work, a novel entropy extraction method is used to improve throughput of jitter-based true random number generators on FPGA. By utilizing ultra-fast carry-logic primitives available on most commercial FPGAs, we have improved the efficiency of the entropy extraction, thereby increasing the throughput, while maintaining a compact implementation. Design steps and techniques are illustrated on an example of a ring-oscillator based true random number generator on Spartan-6 FPGA. In this design, the required accumulation time is reduced by 3 orders of magnitude compared to the most efficient oscillator-based TRNG on the same FPGA. The presented implementation occupies only 67 slices, achieves a throughput of 14.3 Mbps and it is provided with a formal evaluation of security.

Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising non-volatile memory technologies and shows potential as an SRAM replacement. However, targeted for advanced CMOS technologies such as the 14nm FinFET node, time-zero variability is a major concern for these memory technologies. In this paper, we investigate the STT-MRAM variability with respect to different technology scenarios. We show the impact of these variations on the bit error rate of the emerging STT-MRAM memories.

This paper proposes a novel integrated oscillator topology based on a transmission line. The frequency is extracted from the delay of the transmission line, which is intrinsically independent of temperature and supply variations. The architecture for the oscillator, guidelines for the design of the transmission line as well as the different building blocks are presented. The architecture is based on a phase-locked loop topology. The transmission line used has a 509 ps delay, an area of 2.26 mm2and a 4.38 dB power loss. The effect of process variations on the transmission line is extensively investigated. A digital driver using CMOS inverters and an analog driver based on an OTA are proposed. Both have a good stability over temperature. The Gilbert cell is proposed as a detector at the output of the transmission line and the corresponding design considerations are shown. Closed loop simulations show fast locking, a variation of 8.3°C between -10°C and 85°C and a variation of 3.70/00for Vdd± 10%.

Radio communication exhibits the highest energy consumption in wireless sensor nodes. Given their limited energy supply from batteries or scavenging, these nodes must trade data communication for on-the-node computation. Currently, they are designed around off-the-shelf low-power microcontrollers. But by employing a more appropriate processing element, the energy consumption can be significantly reduced. This paper describes the design and implementation of the newly proposed folded-tree architecture for on-the-node data processing in wireless sensor networks, using parallel prefix operations and data locality in hardware. Measurements of the silicon implementation show an improvement of 10-20× in terms of energy as compared to traditional modern micro-controllers found in sensor nodes.

A low-power and low-voltage BBPLL-based sensor interface for resistive sensors in Wireless Sensor Networks is presented. The interface is optimized towards low power, fast start-up time and fast conversion time, making it primarily useful in autonomous wireless sensor networks. The interface is time/frequency-based, making it less sensitive to lower supply voltages and other analog non-idealities, whereas conventional amplitude-based interfaces do suffer largely from these non-idealities, especially in smaller CMOS technologies. The sensor-to-digital conversion is based on the locking behavior of a digital PLL, which also includes transient behavior after start-up. Several techniques such as VDDscaling, coarse and fine tuning and pulse-width modulated feedback are implemented to decrease the transient and acquisition time and the power to optimize the total energy consumption. In this way the sensor interface consumes only 61µW from a 0.8V DC power supply with a one-sample conversion time of less than 20µs worst-case. The sensor interface is designed and implemented in UMC130 CMOS technology and outputs 8 bit parallel with 7.72 ENOB. Due to its fast start-up time, fast conversion time and low power consumption, it only consumes 5.79 pJ/bit-conversion, which is a state-of-the-art energy efficiency compared to recent resistive sensor interfaces.

Recently, multiple non-volatile emerging memories (NVMs) have been proposed and show promising properties to replace SRAM-based memories in future SoCs. However, these new emerging memories, such as STT-MRAM and ReRAM, provide new challenges for the processor design e.g. larger write latencies, higher power and lower endurance. In this paper, we propose a design method for memristor-based (ReRAM) memory architectures for embedded processors to address the effects caused by longer write latencies. We evaluate this method and present the design space for using ReRAM in the data memory of an wireless base band processor. We propose architectural solutions for concealing the slow write speed of ReRAM and show their trade-offs in terms of performance with respect to different write latencies. We show that for single benchmarks the performance penalty caused by the ReRAM write latency can be reduced to 7% for the complete wireless communication benchmark suite. Morevoer, for single benchmarks the performance penalty can be eliminated completely.

This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability resilient WRITE operation and improves the degraded access speed of SRAM cells at low voltages. Differential VSS bias increases the variability resilience. The physical regularity in the layout of local assist circuitry enables litho optimization thereby reducing the area overhead associated with existing local assist techniques. Statistical simulations in 40nm LP CMOS technology reveals 10x reduction in WRITE energy consumption, 103x reduction in write failures, 6.5x improvement in read access time and 31% reduction in the area overhead.

Wireless sensor nodes require low-energy components given their limited energy supply from batteries or scavenging. Currently, they are designed around off-the-shelf low-power microcontrollers for on-the-node processing. However, by employing more appropriate hardware, the energy consumption can be significantly reduced. This paper identifies that many WSN applications employ algorithms which can be solved by using parallel prefix-sums. Therefore, an alternative architecture is proposed to calculated them energy-efficiently. It consists of several parallel processing elements (PEs) structured as a folded tree. Profiling SystemC models of the design with ActivaSC helps to improve data-locality. Measurements of the fabricated chip confirm an improvement of 10-20x in terms of energy as compared with traditional MCUs found in sensor nodes.

An essential part of the bachelor program in Electrical Engineering at the Katholieke Universiteit Leuven since many years is a number of design projects that teach the basics of electronics design engineering to our students. The major project consists of an academic-year-long design task that is carried out by a group of about 20 students. These students are trained to operate as a multidisciplinary team based of sub- teams that handle the different design problems in a multidisciplinary way. Teaching assistants are added to the team to serve either as expert designer or as project leader of a team. In this way the students learn a lot about the circuits, systems and software they conceive but they also develop their teamwork, leadership and presentation skills. In this paper we will give an overview of the technical content of this project and describe the way how it is organised. Taking this project as an example, the rationale behind this kind of interdisciplinary design projects is depicted.

In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked dies (tiers). This allows redesigning the memory tier as a configurable product to be used in multiple system designs. Previously proposed dynamic re-configurable solutions demonstrate strong dependence between read latency and dimensions of the mapped memory, leading to potential performance limitations. In this paper we propose a one-time configurable memory tier designed to minimize the performances overhead due to the commodity. Flexible configuration is enabled by smart memory macros and I/Os organization and a customizable redistribution layer routing. With respect to the dynamic re-configurability, the proposed design offers up to 40% faster access time, while saving more than 10% of energy per access. In addition production cost trade offs are analyzed.

Voltage-controlled oscillator-based analog-to-digital converters utilizes the superior time resolution and digital processing power of time-domain signal processing. With its inherent first-order noise shaping property, very high accuracy can be obtained while reducing both area and power consumption. An all-digital VCO-based ADC scheme is presented which combines a differential configuration with digital calibration to obtain very high linearity. A coarse-fine quantization approach is used to reduce the circuit complexity compared to the traditional multi-bit quantization The phase resolution is increased using passive interpolation coupled VCOs. These techniques are illustrated with a 65 nm CMOS implementation of a 30 MHz BW 10-bit ADC, occupying only 0.023 mm2.

RF-powered wireless sensor networks demand for ultra-low-energy A/D converters. Such systems have specific requirements, like fast start-up time and supply voltage independence. The presented A/D converter is based on a digital phase locked loop. Two closely matched ring oscillators perform the analog to frequency conversion. The digital output is generated by an in-loop digital proportional-integral filter. The acquisition of the PLL is splitted into coarse and fine tuning to reduce the locking time to less than 30μs. A UMC130 CMOS technology is used to simulate a temperature sensor interface. The energy consumption is maximally 212 pJ per conversion and the effective number of bits is 7 bit in a 0.5 V-1.4 V supply voltage range.

Today's highly integrated System-on-Chips (SoC) demand innovative architectural modeling means to cope with their energy constraints. In this context, SystemC has become a well-established simulation tool for Transaction Level Modeling (TLM) in the integrated electronics industry but it lacks the support for power modeling. This paper introduces ActivaSC, a flexible, fast, transparent and non-intrusive extension to the SystemC class library which allows capturing the activity information of a digital system being modeled. This information can then be post-processed to estimate power consumption. ActivaSC avoids time consuming design iterations as designers can assess architectural design trade-offs based on system activity early in the design flow. ActivaSC does not require any code alterations nor a specific API, so that it can be used with any modeling style. Finally, several benchmark tests illustrate the superior efficiency of ActivaSC. A speed-up of up to 75% in terms of elaboration overhead and 20% in terms of simulation overhead is realized with respect to prior art.

Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption. The existing solution for the memory bottle-neck is to increase the amount of on-chip memory. However, this solution is becoming prohibitively expensive, allowing 3D stacked DRAM to become an interesting alternative for mobile applications. In this paper, we examine the power/performance benefits for three different 3D stacked DRAM scenarios. Our high-level memory and Through Silicon Via (TSV) models have been calibrated on state-of-the-art industrial processes. We model the integration of a logic die with TSVs on top of both an existing DRAM and a DRAM with redesigned transceivers for 3D. Finally, we take advantage of the interconnect density enabled by 3D technology to analyze an ultra-wide memory interface. Experimental results confirm that TSV-based 3D integration is a promising technology option for future mobile applications, and that its full potential can be unleashed by jointly optimizing memory architecture and interface logic.

This paper presents a DRAM architecture that improves the DRAM performance/power trade-off to increase their usability on low power chip design using 3D interconnect technology. The use of a finer matrix subdivision and buffering the bitline signal at the localblock level allows to reduce both the energy per access and the access time. The obtained performances match those of a typical low power SRAM, while achieving a significant area and static power reduction compared to these memories. The 128 kb memory architecture proposed here achieves an access time of 1.3 ns for a dynamic energy of less than 0.2 pJ per bit. A localized refresh mechanism allows gaining a factor of 10 in static power consumption associated with the cell, and a factor of 2 in area, when compared with an equivalent SRAM.

It is widely acknowledged that three-dimensional (3-D) technologies offer numerous opportunities for system design. In recent years, significant progress has been made on these 3-D technologies, and they have become probably the best hope for carrying the semiconductor industry beyond the path of Moore's law. However, a clear roadmap is missing to successfully introduce this 3-D technology onto the market. Today, a plurality of 3-D technology options exists, which requires different design and test strategies. To crystallize the many technology options in a few mainstream technologies, it is mandatory to coexplore both technology and design options. The contribution of this paper is to introduce a novel path finding methodology to untangle the many intertwined design/technology options. This holistic approach will be applied on a representative 3-D case study. Initial results demonstrate the benefits of the proposed path-finding methodology to steer the technology development and fine-tune design strategies.

This paper presents a formalized synthesis methodology for variable tapered buffer chains achieving Pareto optimal energy-delay (E/D) tradeoffs via the buffer gate sizes and adding supply voltage as an extra tuning knob. In addition, a detailed discussion of the practically achievable tradeoff ranges via the gate size and especially supply voltage tuning is present. We have applied the methodology for the design and fine tuning of the run-time switchable buffers within the Level-1 (L1) embedded SRAMs (eSRAM), confirming that a very wide range in delay and energy reduction (up to 50%) can be achieved when compared to solely optimal speed eSRAM design using conventional high speed buffers.

We present a 3-tier UWB-based indoor localization system. It consists of a large number of energy-scavenging-based cost-effective transmit-only tags, a small number of battery powered hubs as relay stations and a few base stations. This hierarchical scheme is driven by the energy available at each node. Localization is based on the arrival time of the UWB pulses at reference nodes.We describe how the coordinates and transmit time of a tag are determined and how the ambiguous solution is eliminated with the proper geometry of 4 reference nodes. We formulate where to place the hubs as an optimization problem. The localization performance of the system is investigated as a function of several parameters such as non-ideal hub placement, hub localization error and TOA error.

This paper presents a flexible digital receiver for pulsed Ultra-Wideband (UWB) communications which is sampling below Nyquist rate. This receiver can trade demodulation performance for sampling rate, i.e. power consumption. The bit error rate for pulse amplitude and pulse position modulations is evaluated in AWGN and typical UWB channels. The performance of several types of equalizer is compared, taking into account their implementation complexity. A suboptimal but implementation efficient Minimum Mean-Square Error (MMSE) equalizer which reaches performances similar to the ideal MMSE equalizer is proposed. The impact of imperfect knowledge of the propagation channel and signal-to-noise ratio, due to the limited number of training symbols, on the performance of the receiver is assessed. Finally, the receiver architecture and implementation cost are discussed. The proposed subsampling receiver provides an attractive alternative to classical architectures based on correlation with a template.

A flexible digital architecture for a pulsed ultra-wideband demodulator sampling below Nyquist rate is presented. The system is based on a complex Singular Value Decomposition implemented on a configurable systolic array of simple processors. Automatic code generation is applied to cut design time and rapidly assess the implementation cost of several architectures of the processors.

Impulse-radio-UWB is the ideal air interface for low power wireless applications especially when they require ranging capabilities. This paper presents a complete UWB transceiver system, including acquisition and ranging protocols. The system is fully reconfigurable in terms of bandwidth, data rate, processing gain, acquisition protocol and ranging accuracy, in order to fulfill the needs of the application with minimal energy consumption. The complete system is demonstrated by measurements on an IR-UWB transceiver platform built around 3 fully integrated CMOS chips. The transceiver system achieves a data rate up to 50 Mbps and a ranging error with a root mean squared error of less than 10 cm while consuming 31.7 mW. The IC implementation allows to fully validate the power/flexibility trade-off that can be achieved with integrated solutions.

An analog to digital conversion scheme based on an Asynchronous SigmaDelta Modulator is presented. It uses a Time-to-Digital converter to convert the continuous-time square wave signal produced by the Asynchronous SigmaDelta Modulator to a time-quantized digital signal. The original input signal is then recovered by applying a digital demodulation algorithm derived from general duty-cycle modulation theory. This technique shifts the complexity towards the digital domain and is therefore especially suited for ultra-low voltage technologies beyond 90 nm. Simulations show 13 bit accuracy for Bluetooth baseband 500 kHz with a first-order SigmaDelta modulator and a Time-to-Digital Converter with 10 ps resolution running at 12 MHz. Using a second-order feedback system to shape the quantization noise of the Time-to-Digital converter, the bandwidth can be increased to 12 MHz with 12 bit accuracy, suitable for video applications.

This paper introduces a novel receiver architecture for low-power IR-UWB receivers in the 3.75–4.25GHz band. The receiver correlates the incoming pulse with an approximated pulse template in the analog domain. The template is learnt digitally and transferred to the analog domain via a low resolution DAC. The paper presents the design of the mixing DAC that implements the downconverter, DAC and correlator which consumes only 875uW in 90nm CMOS technology. The DAC receiver topology requires 4dB less energy per incoming bit in comparison with current state-of-the-art IR-UWB receivers.

Several EDA surveys confirm that the Mathworks Matlab/Simulink and the unified modelling language (UML) are both gaining increased attention as electronic system level (ESL) languages. While Matlab is commonly used to model signal processing intensive systems, UML has the potential to support innovative ESL methodologies which tie the architecture, design and verification aspects in a unified perspective. Integrated design flows which exploit the benefits of the complementarity between UML and Matlab provide an interesting answer to the issues of mono-disciplinary modeling and the necessity of moving beyond point-tool solutions. This paper summarizes how UML and Matlab/Simulink can be associated and what is the impact of SysML, a new modeling language based on UML to describe complex heterogeneous systems

This paper presents a low power pulsed UWB receiver sampling below Nyquist rate which can accomodate time-varying data rate and quality-of-service requirements for applications communicating via UWB. The performance of pulse amplitude and pulse position modulations is assessed in AWGN and dense multipath environments using the standard IEEE 802.15.3a channel models. The proposed subsampling receiver provides an attractive digital alternative to the classical approach based on analog correlations, and can reach data rates above 100 Mb/s.

This paper starts with a brief introduction to the UML 2.0 and application-specific UML customizations via profiles. After a discussion of UML design tools with focus on EDA support, we present a HW/SW co-design approach and demonstrate how HW architectures are described together with application SW in a unique UML based environment. Using a dedicated profile providing support for SystemC in UML, and a SystemC wrapper for the SimIt instruction set simulator of a StrongARM, an executable model of the complete architecture is generated which can be simulated by the SystemC kernel. The physical layer of an 802.11a system is used as an application example.

Wireless microsensor networks, which have been the topic of intensive research in recent years, are now emerging in industrial applications. An important milestone in this transition has been the release of the IEEE 802.15.4 standard that specifies interoperable wireless physical and medium access control layers targeted to sensor node radios. In this paper, we evaluate the potential of an 802.15.4 radio for use in an ultra low power sensor node operating in a dense network. Starting from measurements carried out on the off-the-shelf radio, effective radio activation and link adaptation policies are derived. It is shown that, in a typical sensor network scenario, the average power per node can be reduced down to 211 /spl mu/W. Next, the energy consumption breakdown between the different phases of a packet transmission is presented, indicating which part of the transceiver architecture can most effectively be optimized in order to further reduce the radio power, enabling self-powered wireless microsensor networks.

This introductory embedded tutorial gives an overview of the design problems at hand when designing integrated electronic systems in nanometer-scale CMOS technologies. First, some general problems that affect circuit design are addressed, such as the increased leakage and variability with scaling technologies. Next, the impact of this on digital circuit design and embedded memories is discussed. Finally, problems bothering embedded analog circuits are presented, such as reducing supply voltages, poor design productivity and signal integrity troubles. Addressing these problems will determine whether the design road ends at CMOS technology marker "65 nm " or not.

UML is gaining increased attention as a system design language, as indicated by current standardization activities such as the SysML initiative and the UML for SoC Forum. Moreover the adoption of UML 2 is a significant step towards a broader range of modeling capabilities. This paper provides an overview of the impact of these recent advances on the application of UML for SoC and NoC development, proposes a model-driven development method taking benefit of the best techniques recently introduced, and investigates the design of power efficient systems with UML.

Variability is becoming a serious problem in process technology for nanometer technology nodes. The increasing difficulty in controlling the uniformity of critical process parameters (e.g. doping levels) in the smaller devices, makes the electrical properties of such scaled devices much less predictable than in the past. In this paper, we study how these technology effects influence the energy and delay of a SRAM module. Despite the implications in the correct operation of the module, in practically all cases the affected memory implementations become also slower while consuming on average more energy than nominally. This is partly counter-intuitive and no existing literature describes this in a systematic generic way for SRAMs. In this paper, we identify and illustrate the different mechanisms behind this unexpected behavior and quantify the impact of these effects for on-chip SRAMs at the 65 nm technology node.

This paper describes a complete system architecture for an ultra-low power, pulsed UWB receiver in the 0-960 MHz band for low data rate communication (10 kbps) in sensor networks, together with its acquisition algorithms and performance evaluation. Power consumption of this receiver is decreased impressively in relation to common fully digital receivers by shifting the matched filter operation to the analog domain, by using efficient acquisition schemes and by introducing extreme parallelism in the baseband. The optimal trade-off between a low power design and a good performance gain is searched. Sub 10 mW active power and sub 10 /spl mu/W standby power are targeted, to achieve an average power consumption (analog + baseband) of 70 /spl mu/W for data rates of 10 kbps, while realizing a processing gain of almost 30 dB.

This paper presents a novel formalized technique for variable tapered buffer design achieving Pareto optimal energy-delay tradeoffs. Our main focus lies on the drivers typically found in embedded SRAMs. Much work has been done for variable tapered buffer design explicitly targeting energy (and/or area) tradeoffs for a given target delay. In contrast, the formalized techniques presented here are capable of providing all existing Pareto configurations achieving optimal energy/delay tradeoffs, and this is applicable for the full range of all possible delay constraints. Based on such techniques, a transistor-level implementation is also presented to allow a discrete set of Pareto configurations (from high-speed to low-energy) to be selected at run-time. This implementation has been validated via SPICE simulations for a 65-nm CMOS technology, confirming that a very wide range in delay (more than a factor 2) and energy consumption (up to 40%) can be achieved at the SRAM level, including process variability impact effects present in CMOS nanometer technologies.

This paper compares different receiver architectures for UWB radio communication in the 3.1-5GHz band, targeting data rates up to 10Mbps, in terms of their BER performance and power consumption. A receiver, in which some correlations are carried out in the analog domain seems to outperform a fully digital receiver, commonly suggested for baseband UWB. This paper proves that for equal processing gain requirements the partially analog receiver consumes 7 times less power per received bit than the fully digital one.

This paper focuses on co-simulation scenarios and their applications as a part of a system-on-chip (SoC) modeling and design methodology developed at Alcatel Microelectronics (now part of STMicroelectronics) within a wireless local area network (LAN) SoC project. This methodology proposes to build a SystemC-based executable model of the system to maintain a bridge between the algorithmic and the implementation worlds. The model is used in later phases by means of co-simulation of SystemC, HDL and firmware. SystemC-HDL co-simulation scenario provides a way of checking inter-operability of a single designed HW module with the SystemC model. The SystemC-instruction set simulator (ISS) co-simulation provides a platform to develop and verify the firmware that will run on the selected processor core even before the HW modules are designed. It is shown that, with sufficient tool support, these design stages reduce the complexity of the SoC design and improve the debugging capabilities.