The accurate classification of plant growth stages from image sequences is a challenging problem due to the gradual and continuous nature of plant development. Significant variability exists within the same category of growth, and temporal boundaries between successive categories often exhibit visual similarities, complicating the classification task. Whereas the existing approaches are limited and rely on the analysis of single frames, they do not take temporal information embedded in sequential data, reducing robustness and accuracy. They also show vulnerability to intra-category variability among the images and also to inter-class overlap at the temporal boundaries. To address these challenges, we propose a novel approach, PSO-SqueezeTempVote, for plant temporal state categorisation that combines PSO for hyperparameter optimisation of the SqueezeNet architecture with Temporal Image Sequence Fusion (TISF) for temporal ensemble learning. The PSO part effectively optimises some critical hyperparameters, hence improving the performance of the model on individual frames. Meanwhile, the component of TISF exploits temporal continuity using a sequence of images’ aggregation through majority voting. This enables classifying the segment of an image much more precisely than the previously done approaches. Results on our datasets confirm that the PSOSqueezeTempVot has improved the state-of-the-art techniques by almost 13%, out of which approximately 6% was contributed by TISF itself.

Edge–to–cloud inference for vision based models often stalls on the activation data that must cross the link between an IoT device and its server. This paper integrates Time-dependent Clustering Loss (TCL) with a lightweight, layer-specific novel hybrid L2 + Entropy channel-pruning rule applied exactly at the partition boundary. TCL aligns feature maps to discrete levels, enabling aggressive post-training quantization, while the hybrid pruning criterion removes up to 90 % of channels without noticeable accuracy loss.Experiments on ResNet50, EfficientNetV2-S, and YOLOv10n running on a Jetson Orin Nano node demonstrates clear gains across three realistic uplink capacities. At 100 Mbit s−1, partitioned inference completes in 1.2 ms (ResNet50), 1.1 ms (EfficientNetV2-S) and 2.8 ms (YOLOv10n), yielding approximately 6×, 7× and 18× while speed-ups over an all-server baseline still surpassing full on-device execution. With uplinks of 300 Mbit s−1and 500 Mbit s−1, the communication penalty shrinks, yet the proposed pipeline retains more than 2× acceleration over all-edge processing and limits accuracy degradation to a 1–2 % point drop.Because pruning is confined to a single layer and relies only on post-training activation statistics, integration is simple and incurs negligible overhead. The combined TCL quantization and L2 + Entropy pruning strategy therefore offers a practical, bandwidth-aware solution for deploying modern CNNs in IoT-edge scenarios.

Training artificial neural networks is a fundamental step in developing machine learning models, as it determines their ability to learn and generalise from data. While gradient-based methods such as stochastic gradient descent and its variants dominate training approaches, they are susceptible to issues like sensitivity to initialisation and convergence to local optima. To address these challenges, gradient-free metaheuristic algorithms, such as differential evolution (DE), are promising alternatives due to their ability to effectively explore complex optimisation landscapes. In this paper, we propose a novel DE-based algorithm, PruneClust-DE, for training multilayer neural networks. Our approach introduces two key strategies: (1) clustering-based interpolation, which partitions the population into clusters, identifies centroids, and generates new candidate solutions by interpolating between cluster centroids to balance exploration and exploitation, and (2) fitness-based pruning, a mechanism that retains only the fittest individuals after introducing new candidates, ensuring a constant yet high-quality population. We validate our proposed algorithm across diverse datasets and compare its performance with other state-of-the-art methods, demonstrating its superiority in achieving robust results.

Determining optimal weights and biases for neural networks is a critical task. While gradient-based methods are widely used for training, they are sensitive to initialisation and susceptible to local optima. Population-based metaheuristics, such as differential evolution (DE), can offer a reliable alternative. Recently, clustering-based DE approaches have been proposed to further improve this process. However, they suffer from increased complexity, particularly with growing network sizes, leading to longer computation times. In this paper, we introduce strategies to reduce the time complexity of clustering-based DE, including clustering in the objective space, a two-tier clustering period, and one-step k-means clustering. We select one of the recent training algorithms, C2L-DE, as a representative method to incorporate our proposed strategies, leading to a lightweight version, C2L-DE-Lite. We show that C2L-DE-Lite decreases the complexity from $O\left. {\left({\sqrt {{N_{pop}}} \cdot{N_{pop}}\cdot} \right.d\cdot I}\right)$, where Npopis the population size, d is the dimensionality, and I is the number of iterations, to $O\left({\frac{{{N_{pop}}\cdot\sqrt {{N_{pop}}} }}{{CP}}}\right)$, where CP is the clustering period. This means that the complexity remains constant for increasing sizes of networks. Extensive experiments demonstrate that while significantly reducing time complexity, C2L-DE-Lite maintains similar performance levels.

The efficient management of agricultural resources requires a deep understanding of plant growth dynamics. This research focuses on Sweden's forestry sector and explicitly addresses the crucial early stages of pine tree development. The main difficulty in categorising plant growth over time is that instances within a given category are not identical, while instances from different categories may have similarities. In this context, we present a novel measurement system that integrates the capa-bilities of evolutionary computation and deep transfer learning using image data. The image acquisition system includes a tray of plates that moves through a nursery, generating a dataset captured over 44 days of plant growth. Our newly proposed algorithm, EvoSqueezeNet, employs various search strategies for SqueezeNet deep transfer learning to find proper hyper-parameters. We opted for SqueezeNet based on our preliminary studies, revealing its superior performance compared to other pre-trained models in our case study. Given that our approach is independent of any specific evolutionary algorithm, we utilised five distinct search strategies. These include Differential Evolution (DE), Particle Swarm Optimisation (PSO), Covariance Ma-trix Adaptation Evolution Strategy (CMA-ES), Comprehensive Learning PSO (CLPSO), and Linear Population Size Reduction Success-History Adaptation DE (LSHADE). Consequently, we proposed five EvoSqueezeNet schemes for temporal plant growth categorisation. One characteristic of our proposed model is that it uses a limited computation budget for search strategies, en-hancing its applicability in real-world applications. The proposed EvoSqueezeNet methodology demonstrates an error reduction of more than 40%, showcasing its superior performance compared to competing methods.

Methods for estimating the remaining useful life of bearings are of great value in preventing them from failing. Because of this, different types of methods have been suggested. One of the most prominent is transfer learning since it achieves high performance despite the discrepancies in data expected in industrial applications. However, most current research ignores aspects such as the influence of non-bearing related faults, the non-existence of historical run-to-failure data from the target domain and knowledge transfer between machines. Considering this, how existing methods will cope with these scenarios is not established. Therefore, this study examines the performance of transfer learning methods based on current studies methodolo-gies. The result suggests that there are limitations to the assumptions made in the current research and that more considerations for scenarios found in industrial applications are needed both in the development and evaluation phases to increase the possibility of applying transfer learning methods in practice.

Many wireless vision sensor networks (WVSNs) applications are characterized to have a low duty cycling. An individual wireless vision sensor node (VSN) in WVSN is required to complete the tasks as quickly as possible. The execution of the tasks can be speeded up by exploiting the inherited parallelism in the tasks by using a hardware platform such as field-programmable gate array (FPGA). Traditionally, SRAM FPGAs are considered to be inefficient for duty cycled applications. This paper presents a low-complexity, energy-efficient, and reconfigurable VSN architecture based on SRAM FPGA using a design matrix, which includes tasks' partitioning, a low-complexity background subtraction, bilevel coding, and duty cycling. The proposed VSN, referred to as SENTIOF-CAM, has been implemented on a prototype board and energy values of different states are measured for three real applications. The comparison results with existing solutions show that the proposed architecture with SRAM FPGA can achieve energy reduction of up to a factor of 69 as compared with software VSN solutions and approximately similar energy values to that for the FLASH FPGA-based VSN solutions. The lifetime based on measured energy values shows that, for a sample period of 5 min, a 3.2-years lifetime can be achieved with a battery of 37.44-kJ energy. In addition, the proposed solution offers a generic architecture with a smaller design complexity on a hardware reconfigurable platform and offers easy adaptation for a number of applications.

Wireless vision sensor nodes consist of limited resources such as energy, memory, wireless bandwidth and processing. Thus it becomes necessary to investigate lightweight vision tasks. To highlight the foreground objects, many machine vision applications depend on the background subtraction technique. Traditional background subtraction approaches employ recursive and non-recursive techniques and store the whole image in memory. This raises issues like complexity on hardware platform, energy requirements and latency. This work presents a low complexity background subtraction technique for a hardware implemented wireless Vision Sensor Node (VSN). The proposed technique utilizes existing image scaling techniques for scaling down the image. The downscaled image is being stored in internal memory of hardware platform. For subtraction operation, the background pixels are generated in real time with up a scaling technique. The performance, and memory requirements of the system is compared for four image scaling techniques including nearest neighbor, averaging, bilinear, and bicubic. The results show that a system with lightweight scaling techniques, i.e., nearest neighbor and averaging, up to a scaling factor of 8, missed on average less than one object as compared to a system which uses a full original background image. The proposed approach will reduce the memory requirement by a factor of up to 64 besides reduction in design/implementation complexity and cost as compared to background model which involve whole frame.

Wireless Visual Sensor Network (WVSN) is formed by deploying many Visual Sensor Nodes (VSNs) in the field. The VSNs acquire images of the area of interest in the field, perform some local processing on these images and transmit the results using an embedded wireless transceiver. The energy consumption on transmitting the results wirelessly is correlated with the information amount that is being transmitted. The images acquired by the VSNs contain huge amount of data due to many kinds of redundancies in the images. Suitable bi-level image compression standards can efficiently reduce the information amount in images and will thus be effective in reducing the communication energy consumption in the WVSN. But compression capability of the bi-level image compression standards is limited to the underline compression algorithm. Further data reduction can be achieved by detecting Region of Interest (ROI) in the bi-level images and then coding these ROIs using bi-level image compression method. We explored the compression performance of the lossless ROI detection and coding method for various kinds of changes such as different shapes, locations and number of objects in the continuous set of frames. The CCITT Group 4, JBIG2 and Gzip are used for coding the detected ROIs. We concluded that CCITT Group 4 is a better choice for coding the ROIs in the Bi-level images because of its comparatively good compression performance and less computational complexity. This paper is intended to be a resource for the researchers interested in reducing the amount of data in the bi-level images for energy constrained WVSNs.

Wireless vision sensor networks (WVSNs) have a number of wireless vision sensor nodes (VSNs), often spread over a large geographical area. Each node has an image capturing unit, a battery or alternative energy source, a memory unit, a light source, a wireless link, and a processing unit. The challenges associated with WVSNs include low energy consumption, low bandwidth, limited memory, and processing capabilities. In order to meet these challenges, our paper is focused on the exploration of energy-efficient reconfigurable architectures for VSN. In this paper, the design and research challenges associated with the implementation of VSN on different computational platforms, such as microcontroller, field-programmable gate arrays, and server, are explored. In relation to this, the effect on the energy consumption and the design complexity at the node, when the functionality is moved from one platform to another, are analyzed. Based on the implementation of the VSN on embedded platforms, the lifetime of the VSN is predicted using the measured energy values of the platforms for different implementation strategies. The implementation results show that an architecture, where the compressed images after pixel-based operation are transmitted, realize a WVSN system with low energy consumption. Moreover, the complex postprocessing tasks are moved to a server which has less constraints.

Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have proven to be effective implementation architecture for these systems. However, the hardware based design flow for FPGAs make the implementation task complex. The system synthesis tool presented in this paper reduces this design complexity. The synthesis is done from a SystemC based coarse grain dataflow graph that captures the video processing system. The data flow graph is optimized and mapped onto an FPGA. The results from real-life video processing systems clearly show that the presented tool produces effective implementations.

The great variety of pixel dynamics of real-time video-processing systems (RTVPS), ranging from color, grayscale, or binary pixels, means that a careful design and specification of bit widths is required. It is obvious that the bit-width specification will affect the total memory storage requirement. However, what is not so obvious is that the bit-width specification will also affect the design of the memory hierarchy, an impact similar for both hardware and software implementations. We have developed an integer-nonlinear-program formulation for the optimization of the memory hierarchy of RTVPS. An active surveillance video camera is introduced as a test case. We demonstrate how the optimization model can reduce the on-chip memory storage by 61% compared to a nonoptimal memory hierarchy.

Bit-width specification will affect the total memory storage requirement of a video processing system. However, what is not so obvious is that the bit-width specification will also affect the design of the memory hierarchy. Experiments with a real-life surveillance system show how the optimal allocation of shift registers for the storage of intermediate results is sensitive to bit-widths. It is shown that the total on-chip memory storage requirement can be reduced by 61 percent compared to a non-optimal design

FPGA offers the potential of being a reliable, and high-performance reconfigurable platform for the implementation of real-time video processing systems. To utilize the full processing power of FPGA for video processing applications, optimization of memory accesses and the implementation of memory architecture are important issues. This paper presents two approaches, base pointer approach and distributed pointer approach, to implement accesses to on-chip FPGA Block RAMs. A comparison of the experimental results obtained using the two approaches on realistic image processing systems design cases is presented. The results show that compared to the base pointer approach the distributed pointer approach increases the potential processing power of FPGA, as a reconfigurable platform for video processing systems.

We present a method for generation of the software part of a HW/SW interface (i.e. the device drivers), which separates the behaviour of the interface from the architecture dependent parts. We do this by modelling the behaviour in ProGram (a grammar based protocol specification language) and capture the processor and OS kernel parts in separate libraries. By separating the behaviour from the architectural specific parts, compared to other approaches up to 50% development time can be saved the first time the component is used, and up to 98% for each time the interfaced component is reused.