Due to high-density implementation, large-capacity routers are very heavy and consume a huge amount of power. Such routers require the capability for power-supply and air-cooling equipment to be increased. Upon introducing such routers, the physical limitations of the infrastructure should be considered. In addition, wider space in machine rooms to maintain reliability criteria is required, even though space is a precious resource and the purpose of high-density routers is to save floor space. We describe earthquake resistance of high weight, power-supply stability of high power-supply current, and air-cooling reliability of high power consumption. We propose solutions for improved cabinets and power-supply devices and the allocation of this equipment to satisfy network reliability, such as earthquake resistance, power-supply stability, and continuous duration after air-cooling stops. This leads to saving floor area space.

We propose a virtual network edge architecture with a novel wavelength channel add/drop multiplexer configuration using virtualized network functions (VNFs) to save processor and bandwidth resources. The feature of this architecture is VNF live migration with wavelength-division-multiplexing/time-division multiplexing photonic switching technology to use metro network resources efficiently. To reduce the computation of reallocation, the live-migration of a VNF is limited to part of the VNF that contains a larger number of subscribers.

Power consumption of network (NW) equipment has been rapidly increasing; therefore it is necessary to build a resource-efficient NW. Router virtualization, which involves dynamically re-allocating virtual routers to physical resources as server virtualization, is becoming more common as a method of using NW equipment effectively and robustly. Edge routers which are gateways of core NWs should be virtualized because they have many functions and resources just as servers do. A metro NW is a wide area layer-2 aggregation NW that connects each user's residential gateway to edge routers. To achieve edge router virtualization, the metro NW must trace dynamic edge router re-allocation by changing the route of each Ethernet flow. Therefore, we previously proposed a virtual layer-2 switch architecture with scale-out control that can improve route control performance to trace dynamic virtual router re-allocation to use metro NW equipment effectively and robustly. The routes are controlled in parallel flow-by-flow on this architecture. When edge router failure occurs, the controller must change the routes of all flows passing through the failed edge router. On the other hand, load imbalance of this route change occurs among parallel processes. If we can distribute this load evenly, we can decrease resources for the controller deployed in advance. Therefore, in this paper we propose two re-allocation methods for allocating flows to parallel processes according to the virtual router re-allocation. We evaluated the methods through simulation and showed that they can evenly distribute load among parallel processes not only in large-scale metro NWs, but also in data center NWs, which have recently become an important type of large-scale layer-2 NW.

Power consumption of network equipment has been rapidly increasing, so it is therefore necessary to build a resource efficient network (NW). Router virtualization, which involves dynamically reallocating virtual routers to physical resources as a server virtualization, is becoming more common as a way to use network equipment effectively and robustly. Especially, edge router which is gateway of core network should be virtualized, because edge routers have many functions and resources just as servers do. A metro NW is wide area layer-2 aggregation NW that connects each user's residential gateway to edge routers. To achieve edge router virtualization, the metro NW must trace the dynamic edge router reallocation by changing a route of each Ethernet flow. Furthermore, access/metro NWs occupy a large proportion of the total NW power consumption, so logically centralized control architecture suits to the metro NW to change routes flexibly because it can use resources effectively by avoiding resource deployment in many locations. However, it is not scalable. When many Ethernet flows need to be accommodated in a metro NW, it can not change routes of the flows quickly enough. Therefore, we propose a virtual wide area layer-2 switch architecture with scale-out control that can improve the route control performance even in a worst case edge router node failure by processing in parallel flow-by-flow, by considering route information, and by rebalancing the load between parallel processes dynamically. We evaluated the proposed architecture through theoretical analysis and experiments with prototype. The results showed that the proposed architecture can increase the number of flows accommodated in a metro NW.

Although the Internet is playing an increasingly significant role in global communication, it remains vulnerable to malicious traffic such as worms and DoS/DDoS attacks. In the last few years, the emergence of high speed active worms, such as Code Red II, Nimda, SQL Slammer and MS Blaster, has become a serious issue. These worms cause serious damage to communication networks throughout the world by using up network bandwidth. In addition, since conventional firewall systems are located just in front of the server and do not prevent malicious traffic from entering the network, they cannot prevent such network congestion. We have developed a proto-type system of a network firewall using reconfigurable processors. In this paper, we overview the developed system and present its evaluation results.

The paper describes multi-layer traffic engineering and signaling technologies in photonic-GMPLS-router networks. Multi-layer traffic engineering, which yields the dynamic cooperation of IP and photonic layers for providing IP services cost-effectively, is described. To realize multi-layer traffic engineering, we propose an OSPF extension that advertises both the number of total wavelengths and the number of unused wavelengths and an RSVP-TE extension that minimizes the number of wavelength conversions needed. In addition, the paper presents a heuristic-based multi-layer topology design scheme that uses IP traffic measurements in a generalized multiprotocol label switch (GMPLS). Our design scheme yields the optical label switch path (OLSP) network topology, i.e. OLSP placement, that minimizes network cost, in response to fluctuations in IP traffic demand. In other words, the OLSP network topology is dynamically reconfigured to match IP traffic demand. Networks are reconfigured by the proposed scheme so as to utilize the network resources in the most cost-effective manner.

This paper describes a project dedicated to developing an improved (in terms of usability) version of our previous telecommunication-oriented field programmable gate array (FPGA), and its applications. To achieve this goal, we adopt several challenging design strategies. First, we determine the new FPGA architecture based on a quantitative evaluation carried out to optimize the interaction between the FPGA and CAD algorithms. In addition, we create a new chip design environment that allows semi-automatic test pattern generation and cross-checking between logic and layout design. Furthermore, a dedicated CAD system is developed based on a consideration of the evaluation results and the characteristics of the FPGA. As a result of these design strategies, the FPGA and CAD system are well-balanced, and even though the FPGA has very rich routing resources, the routing process can be finished quickly without sacrificing application-circuit performance. The FPGA is applied to several reconfigurable systems for telecommunications, and is found to offer the required functions and good performance.

The paper describes a transmutable telecom system called ATTRACTOR, which uses more than 100 FPGAs, and features both reconfigurability and high performance. There are two key innovations. One is the board-level modularity concept that allows different functions to be implemented on different boards individually. The other is a high-speed serial link mechanism that provides excellent inter-board communication without sacrificing performance. Thus this system can be completely reconstructed to suit different applications by arranging different board combinations and reconfiguring each board. Using ATTRACTOR, we realized an IP packet forwarder, which is very speed-intensive telecom function, that has to decide the next-hop address of each incoming IP packet and send it out on-the-fly. It was confirmed that the function works well in a real ATM-LAN environment.

In designing FPGAs, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has Look-Up Tables (LUTs), and wiring resources. It is difficult to find an optimal solution. In this paper, w e presen t an FPGA design methodology to efficiently find well-balanced FPGA architectures. The method covers all aspects of FPGA development from the architecture-decision process to physical implementation. It has been used to develop a new FPGA that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. This indicates that the methodology is effectiv e in dev eloping well-balanced FPGAs.