Clock grids are often used in high-performance ASIC designs because of their low skew and robustness to variations. Resonant clock grids have the potential to reduce the power consumption of these high-performance clocks without sacrificing the skew and robustness of a clock grid. We present the first methodology to synthesize high-performance distributed resonant LC tank clock grids that utilize a pre-characterized inductor library. The use of a library reduces designer effort and total inductor area when compared with previous resonant clock grids while still attaining 59% power reduction and competitive skew when compared to traditional buffered clock grids.

Resonant clocking is a form of adiabatic clocking that retains much of the energy present in clock switching and recycles it into the following clock cycle. In this paper we present the first automated methodology using LC-assisted local clock buffers (LCLCB) for generating local resonant clocks. This uses a single-buffer single-inductor sector topology applied to non-uniform trees as found in most ASIC designs. We show that this form of adiabatic clocking can achieve power savings as much as 75% over traditional buffered clock networks.