Modern embedded platforms need sophisticated resource managers in order to utilize the heterogeneous computational resources efficiently. Moreover, such platforms are exposed to fluctuating workloads unpredictable at design time. In such a context, predicting the incoming workload might improve the efficiency of resource management. But is this true? And, if yes, how significant is this improvement? How accurate does the prediction need to be in order to improve decisions instead of doing harm? By proposing a prediction-based resource manager aimed at minimizing energy consumption while meeting task deadlines and by running extensive experiments, we try to answer the above questions.

Platforms that are based on heterogeneous architectures require an intelligent resource manager. An intelligent resource manager should be able to accurately predict the future workload of the system at hand and take it into consideration. In this paper, we show that there exist patterns in the interarrival times of resource requests, and that these patterns can be used for modeling and prediction of the future arrivals. To this end, we develop a two-phase machine-learning-based framework and apply it to real data. First, in the offline phase of our framework, the interarrival times are clustered based on a number of extracted features, and then an adequate modeling and prediction method is selected for each detected cluster. It is shown that, due to the intricate and varied nature of interarrival times, a universal modeling and prediction method does not provide optimal results, and a customized method should be applied to each of the detected clusters. Second, in the runtime phase of our framework, the results provided from the offline phase are used to perform computationally cheap prediction. The experimental results show that our approach has a prediction error below 12% and provides an error reduction of more than 17% in comparison with a straightforward method.

We present a framework for system-level analysis of electronic systems whose runtime behaviors depend on uncertain parameters. The proposed approach thrives on hierarchical interpolation guided by an advanced adaptation strategy, which makes the framework general and suitable for studying various metrics that are of interest to the designer. Examples of such metrics include the end-to-end delay, total energy consumption, and maximum temperature of the system under consideration. The framework delivers a light generative representation that allows for a straightforward, computationally efficient calculation of the probability distribution and accompanying statistics of the metric at hand. Our technique is illustrated by considering a number of uncertainty-quantification problems and comparing the corresponding results with exhaustive simulations.

Electronic system designs that ignore process variation are unreliable and inefficient. In this paper, we propose a system-level framework for the analysis of temperature-induced failures that considers the uncertainty due to process variation. As an intermediate step, we also develop a probabilistic technique for dynamic steady-state temperature analysis. Given an electronic system under a certain workload, our framework delivers the corresponding survival function, founded on the basis of well-established reliability models, with a closed-form stochastic parameterization in terms of the quantities that are uncertain at the design stage. The proposed solution is exemplified considering systems with periodic workloads that suffer from the thermal-cycling fatigue. The analysis of this fatigue is a challenging problem as it requires the availability of detailed temperature profiles, which are uncertain due to the variability of process parameters. To demonstrate the computational efficiency of our framework, we undertake a design-space exploration procedure to minimize the expected energy consumption under a set of timing, thermal, and reliability constraints.

We present a framework for the analysis of process variation across semiconductor wafers. The framework is capable of quantifying the primary parameters affected by process variation, e.g., the effective channel length, which is in contrast with the former techniques wherein only secondary parameters were considered, e.g., the leakage current. Instead of taking direct measurements of the quantity of interest, we employ Bayesian inference to draw conclusions based on indirect observations, e.g., on temperature. The proposed approach has low costs since no deployment of expensive test structures might be needed or only a small subset of the test equipments already deployed for other purposes might need to be activated. The experimental results present an assessment of our framework for a wide range of configurations.

Electronic system design based on deterministic techniques for power-temperature analysis is, in the context of current and future technologies, both unreliable and inefficient since the presence of uncertainty, in particular, due to process variation, is disregarded. In this paper, we propose a flexible probabilistic framework targeted at the quantification of the transient power and temperature variations of an electronic system. The framework is capable of modeling diverse probability laws of the underlying uncertain parameters and arbitrary dependencies of the system on such parameters. For the considered system, under a given workload, our technique delivers analytical representations of the corresponding stochastic power and temperature profiles. These representations allow for a computationally efficient estimation of the probability distributions and accompanying quantities of the power and temperature characteristics of the system. The approximation accuracy and computational time of our approach are assessed by a range of comparisons with Monte Carlo simulations, which confirm the efficiency of the proposed technique.

In this paper we propose an analytical technique for the steady-state dynamic temperature analysis (SSDTA) of multiprocessor systems with periodic applications. The approach is accurate and, moreover, fast, such that it can be included inside an optimization loop for embedded system design. Using the proposed solution, a temperature-aware reliability optimization, based on the thermal cycling failure mechanism, is presented. The experimental results confirm the quality and speed of our SSDTA technique, compared to the state of the art. They also show that the lifetime of an embedded system can significantly be improved, without sacrificing its energy efficiency, by taking into consideration, during the design stage, the steady-state dynamic temperature profile of the system.