Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.

A new antilog–sum algorithm for decoding error-correcting codes is described. The soft-input, soft-output (SISO) algorithm uses squared Euclidean distance as the metric, does not require knowledge of the signal-to-noise ratio of the received signal and is less complex to implement than other SISO algorithms. The results of simulations show that the performance is very close to that of the log–sum–product algorithm.

Two product array codes are used to construct the$(24, 12, 8)$binary Golay code through the direct sum operation. This construction provides a systematic way to find proper$(8, 4, 4)$linear block component codes for generating the Golay code, and it generates and extends previously existing methods that use a similar construction framework. The code constructed is simple to decode.

The design of uniquely decodable DC-free multi-user coding schemes with good rate sums for the multiple access adder channel is described in this paper. It is shown that by using the direct sum construction on short multi-user codes, it is possible to devise longer DC-free multi-user coding schemes with rate sums which increase quite rapidly at each iteration of the construction. Asymptotically, there is no penalty in requiring the coding schemes to be DC-free. In addition, the schemes can be efficiently soft decision decoded using a relatively low complexity sectionalised trellis.

This correspondence presents sequential algorithms for soft decision decoding of linear block codes. They use a stack algorithm based on the trellis of the code. We are interested in the trellis as a means to avoid path-decoding repetitions. As well, the possibility of bidirectional decoding offers a chance to increase the likelihood of explored paths. We have developed three successive algorithms that offer a good decrement in the overall complexity, and mainly in the most complex decoding case, while giving near-maximum-likelihood performance. This is important since it determines the maximum buffer size necessary in the decoder.

A novel scarce-state-transition (SST) type trellis decoding system for (n,n-1) convolutional codes with coherent BPSK signals is proposed. The new system retains the same number of binary comparisons as the syndrome-former trellis decoding technique. Like the original SST-type encoder trellis technique, the proposed system is also suitable for CMOS VLSI implementation. A combination of the two techniques results in a less complex and low power consumption decoding system.

Two families of binary linear multiple-burst-correcting array codes are presented. The codes consist of all possible n/sub 1/*n/sub 2/ arrays over GF(2), where the columns have even parity and the rows belong to any given code of length n/sub 2/ and minimum distance 2t. It is shown that if the bits are read out diagonally instead of horizontally, each diagonal followed by the preceding one (viewed cyclically), then the code can correct up to t bursts of lengthor=tn/sub 1/+1. If each diagonal is followed by the next one, the code can correct up to t bursts of lengthor=2t(n-2)+1. For t=1 some of these results are already known. Decoding algorithms are presented, and the case t=1 is discussed in more detail.>

The usual(k_{2} + 1) \times (k_{1} + 1)array code, in which the last row and the last column contain redundant bits, can correct any single error. However, if the bits are read diagonally instead of horizontally, the code can correct bursts of errors. It is shown that the(_{k}2 + 1) \times (k_{1} + 1)array code with diagonal readout can correct any burst of length up tok_{1}if and only ifk_{2} \geq 2(k_{1} - 1).

The tanlock modification of the phase detector characteristics of a phase-lock loop can be used to increase the linear range of operation of the S-curve of an analog loop, hence increasing the tracking and acquisition ranges without increasing the loop gain. The phase-shift-keying tanlock loop is a realization of this modification for the coherent demodulation and tracking of a PSK suppressed carrier signal. In this paper we consider the PSK-TLL loop performance in the presence of additive noise. The equivalent noise source used with the baseband model of the loop is derived. Both linear and quasi-linear approximations are considered for evaluation of the phase error variance (mean-square tracking error) of the loop. The false-lock performance of the PSK-TLL due to distortion of the digital data caused by the limited bandwidth of the arm filters is also considered. Results are obtained for both NRZ and Manchester encoded data symbols.