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Hongbin Zhang 0006

dblp:57/1843-6 · DBLP profile ↗
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4ranked-venue papers
1as first author
4since 2021 · last 2026
0009-0007-9145-3919ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-author · 4 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware accelerators and domain-specific architectures · 40% GPUs and heterogeneous computing · 34% Memory systems · 26%
Artificial intelligence
2 papers
Efficient and distributed learning · 55% Language models and text generation · 46%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Natural language and speech › Language models and text generation
large language model inference
1.012026
Efficient KV Cache Spillover Management on Memory-Constrained GPU for LLM Inference · IEEE Trans. Parallel Distributed Syst. 2026
Machine learning › Efficient and distributed learning › inference efficiency
memory-efficient inference
1.012026
Efficient KV Cache Spillover Management on Memory-Constrained GPU for LLM Inference · IEEE Trans. Parallel Distributed Syst. 2026
GPUs and heterogeneous computing
GPU memory management
1.012026
Efficient KV Cache Spillover Management on Memory-Constrained GPU for LLM Inference · IEEE Trans. Parallel Distributed Syst. 2026
Memory systems › cache management
KV cache management
1.012026
Efficient KV Cache Spillover Management on Memory-Constrained GPU for LLM Inference · IEEE Trans. Parallel Distributed Syst. 2026
GPUs and heterogeneous computing › deep learning on GPUs
GPU inference
0.712023
Improving Computation and Memory Efficiency for Real-world Transformer Inference on GPUs · ACM Trans. Archit. Code Optim. 2023
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.712023
Improving Computation and Memory Efficiency for Real-world Transformer Inference on GPUs · ACM Trans. Archit. Code Optim. 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
transformer inference
0.712023
Improving Computation and Memory Efficiency for Real-world Transformer Inference on GPUs · ACM Trans. Archit. Code Optim. 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
transformer inference accelerator
0.712023
Improving Computation and Memory Efficiency for Real-world Transformer Inference on GPUs · ACM Trans. Archit. Code Optim. 2023
Memory systems
memory management
0.312026
Efficient KV Cache Spillover Management on Memory-Constrained GPU for LLM Inference · IEEE Trans. Parallel Distributed Syst. 2026
Machine learning › Efficient and distributed learning
inference efficiency
0.212023
Improving Computation and Memory Efficiency for Real-world Transformer Inference on GPUs · ACM Trans. Archit. Code Optim. 2023

Methods — techniques the papers use, named apart from their topics

swap orchestration · 2.0response length prediction · 2.0cost modeling · 2.0chunk-based memory management · 1.3batch processing · 1.3
YearPublicationVenuePosition
2026 Efficient KV Cache Spillover Management on Memory-Constrained GPU for LLM Inference
abstract
The rapid growth of model parameters presents a significant challenge when deploying large generative models on GPU. Existing LLM runtime memory management solutions tend to maximize batch size to saturate GPU device utilization. Nevertheless, this practice leads to situations where the KV Cache of certain sequences cannot be accommodated on GPUs with limited memory capacity during the model inference, requiring temporary eviction from GPU memory (referred to as KV Cache spillover). However, without careful consideration of the LLM inference's runtime pattern, current LLM inference memory management solutions face issues like one-size-fits-all spillover handling approach for different platforms, under-utilization of GPU in prefill stage, and suboptimal sequence selection due to direct employment of swap or recomputation. In this paper, we introduce FuseSpill, a holistic KV Cache management solution designed to boost LLM inference on memory-constrained GPU by efficiently handling KV Cache spillover. Specifically, FuseSpill consists of a spillover cost model that analyzes the system cost of spillover handling techniques quantitatively, a KV cache swap orchestrator to further refine the basic swap technique to sophisticated disaggregate KV Cache across heterogeneous devices for decoding iterations, a multi-executor scheduler to effectively coordinate task executors across devices, and a response length predictor to exploit the length-aware sequence selection strategy when KV Cache spillover occurs. The experimental results demonstrate that our implementation outperforms existing solutions, delivering a 20% to 40% increase in throughput while simultaneously reducing the inference latency of the spillover sequences.
Jiazhi Jiang, Yao Chen 0008, Zining Zhang 0001, Bingsheng He, Pingyi Luo, Mian Lu, Yuqiang Chen, Hongbin Zhang 0006, Jiangsu Du, Dan Huang 0001, Yutong Lu
IEEE Trans. Parallel Distributed Syst.8
2025 TD-Pipe: Temporally-Disaggregated Pipeline Parallelism Architecture for High-Throughput LLM Inference
abstract
As the model size continuously increases, pipeline parallelism shows great promise in throughput-oriented LLM inference due to its low demand on communications. However, imbalanced pipeline workloads and complex data dependencies in the prefill and decode phases result in massive pipeline bubbles and further severe performance reduction.
Hongbin Zhang 0006, Taosheng Wei, Zhenyi Zheng, Jiangsu Du, Zhiguang Chen 0001, Yutong Lu
ICPP1
2024 Efficient Coupling Streaming AI and Ensemble Simulations on HPC Clusters
Jiazhi Jiang, Hongbin Zhang 0006, Deyin Liu, Jiangsu Du, Xiaojiao Yao, Jinhui Wei, Pin Chen, Dan Huang 0001, Yutong Lu
Euro-Par (1)2
2023 Improving Computation and Memory Efficiency for Real-world Transformer Inference on GPUs
abstract
Transformer models have emerged as a leading approach in the field of natural language processing (NLP) and are increasingly being deployed in production environments. Graphic processing units (GPUs) have become a popular choice for the transformer deployment and often rely on the batch processing technique to ensure high hardware performance. Nonetheless, the current practice for transformer inference encounters computational and memory redundancy due to the heavy-tailed distribution of sequence lengths in NLP scenarios, resulting in low practical performance. In this article, we propose a unified solution for improving both computation and memory efficiency of the real-world transformer inference on GPUs. The solution eliminates the redundant computation and memory footprint across a transformer model. At first, a GPU-oriented computation approach is proposed to process the self-attention module in a fine-grained manner, eliminating its redundant computation. Next, the multi-layer perceptron module continues to use the word-accumulation approach to eliminate its redundant computation. Then, to better unify the fine-grained approach and the word-accumulation approach, it organizes the data layout of the self-attention module in block granularity. Since aforementioned approaches make the required memory size largely reduce and constantly fluctuate, we propose the chunk-based approach to enable a better balance between memory footprint and allocation/free efficiency. Our experimental results show that our unified solution achieves a decrease of average latency by 28% on the entire transformer model, 63.8% on the self-attention module, and reduces memory footprint of intermediate results by 7.8×, compared with prevailing frameworks.
Jiangsu Du, Jiazhi Jiang, Hongbin Zhang 0006, Dan Huang 0001, Yutong Lu
ACM Trans. Archit. Code Optim.4