Design for low power has become a key requirement in today's System-on-a-Chip design, particularly for mobile applications. Multi-Vdd (MSV) is an effective method to reduce both leakage and dynamic powers. In a MSV design, cells of different supply voltages are often grouped into a small number of voltage islands, in order to avoid complex power-supply system and excessive amount of level shifters. In 2005, Wuetalproposed an elegant algorithm for voltage-island grouping based on the physical proximity of the critical cells in a postplacement voltage assignment and, in 2006, proposed an efficient algorithm for voltage assignment which not only meets timing but also forms good proximity of the critical cells. However, due to insufficient slack, a few isolated critical cells (calledoutliers) may still exist in the resulting voltage assignment, causing disproportionately expensive penalty to the final voltage-island grouping. In this paper, we propose a novel approach to improve the voltage assignment by automatic outlier detection followed by incremental placement. The outlier detection is based on a modified algorithm for the facility-location problem and proper parameter setting. We also propose a novel partial-sort technique which speeds up this algorithm significantly (up to 3times in our experiments). The incremental placement is guided by setting proper constraints on the paths containing the detected outliers, such that the outliers can be eliminated later. Our experiments on industry designs show that our algorithm leads to 12%-54% improvement in the final voltage-island grouping, with quick turn-around time.

Multi-Vdd is an effective method to reduce both leakage and dynamic power. A key challenge in a multi-Vdd design is to control the complexity of the power-supply system and limit the demand for level shifters. This can be tackled by grouping cells of different supply voltages into a small number of voltage islands. Recently, an elegant algorithm was proposed for generating voltage islands that balance the power-versus-design-cost tradeoff under performance requirement, according to the placement proximity of the critical cells. One prerequisite of this algorithm is an initial voltage assignment at the standard-cell level that meets timing. In this article, we present a novel method to produce quality voltage assignment which not only meets timing but also forms good proximity of the critical cells to provide a smooth input to the aforementioned voltage island generation. Our algorithm is based on effective delay budgeting and efficient computation of physical proximity by Voronoi diagram. Our extensive experiments on real industrial designs show that our algorithm leads to 25%--75% improvement in the voltage island generation in terms of the number of voltage islands generated, with computation time only linear to design size.

Design for low power has become a key requirement in today's SoC design, especially for mobile applications. Multi-Vdd is an effective method to reduce both leakage and dynamic power. In a multi-Vdd design, cells of different supply voltages are often grouped into a small number of voltage islands, in order to avoid complex power supply system and excessive amount of level shifters. Recently, [9] proposed an elegant algorithm for voltage island grouping based on the physical proximity of the critical cells in a post-placement voltage assignment, and [10] proposed an efficient algorithm for voltage assignment which not only meets timing but also forms good proximity of the critical cells. However, due to insufficient slack, a few isolated critical cells (called outliers) may still exist in the resulting voltage assignment, causing disproportionately expensive penalty to the final voltage island grouping. In this paper, we propose a novel approach to improve the voltage assignment by automatic outlier detection followed by incremental placement. The outlier detection is based on a modified algorithm for the facility location problem. The incremental placement is guided by setting proper constraints on the paths containing the detected outliers, such that the outliers can be eliminated later. Our experiments on industry designs show that our algorithm leads to 12% -- 54% improvement in the final voltage island grouping, with quick turn around time.

High power consumption not only leads to short battery life for hand-held devices but also causes on-chip thermal and reliability problems in general. As power consumption is proportional to the square of supply voltage, reducing supply voltage can significantly reduce power consumption. Multi-supply voltage (MSV) has previously been introduced to provide finer grain power and performance tradeoff. In this paper, we propose a methodology on top of a set of algorithms to exploit nontrivial voltage island boundaries for optimal power versus design-cost tradeoff under performance requirement. Our algorithms are efficient, robust, and error-bounded and can be flexibly tuned to optimize for various design objectives (e.g., minimal power within a given number of voltage islands, or minimal fragmentation in voltage islands within a given power bound) depending on the design requirement. Our experiment on real industry designs shows a tenfold improvement of our method over current logical-boundary-based industry approach.

Multi-Vdd is an effective method to reduce both leakage and dynamic power. A key challenge in a multi-Vdd design is to limit the design cost and the demand for level shifters. This can be tackled by grouping cells of different supply voltages into a small number of voltage islands. Recently, an elegant algorithm [7] is proposed for generating voltage islands that balance the power versus design cost tradeoff under performance requirement, according to the placement proximity of the critical cells. One prerequisite of [7] is an initial voltage assignment at the standard cell level that meets timing. In this paper, we present a novel method to produce quality voltage assignment to [7], which not only meets timing but also forms good proximity of the critical cells to provide [7] with a smooth input. The algorithm is based on effective delay budgeting and efficient computation of physical proximity by Voronoi diagram. Our extensive experiments on real industrial designs show that our algorithm leads to 25% - 75% improvement in the voltage island generation, with the computation time only linear to the design size.

High power consumption not only leads to short battery life for handheld devices, but also causes on-chip thermal and reliability problems in general. As power consumption is proportional to the square of supply voltage, reducing supply voltage can significantly reduce power consumption. Multi-supply voltage (MSV) has previously been introduced to provide finer-grain power and performance trade-off. In this work we propose a methodology on top of a set of algorithms to exploit non-trivial voltage island boundaries for optimal power versus design cost trade-off under performance requirement. Our algorithms are efficient, robust and error-bounded, and can be flexibly tuned to optimize for various design objectives (e.g., minimal power within a given number of voltage islands, or minimal fragmentation in voltage islands within a given power bound) depending on the design requirement. Our experiment on real industry designs shows a ten-fold improvement of our method over current logical-boundary based industry approach.