Heh-Tyan Liaw

dblp:57/2519 · DBLP profile ↗
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4ranked-venue papers
4as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 90% Performance modeling and evaluation · 10%
Theoretical computer science
1 paper
Computational complexity · 100%

Topics — the 12 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis
boolean function representation
0.011992
On the OBDD-Representation of General Boolean Functions · IEEE Trans. Computers 1992
Electronic design automation › hardware verification and test
hardware verification
0.011992
On the OBDD-Representation of General Boolean Functions · IEEE Trans. Computers 1992
Electronic design automation › logic synthesis › decision diagrams › binary decision diagram
ordered binary decision diagram
0.011992
On the OBDD-Representation of General Boolean Functions · IEEE Trans. Computers 1992
Computational complexity
circuit complexity
0.011992
On the OBDD-Representation of General Boolean Functions · IEEE Trans. Computers 1992
Electronic design automation › hardware verification and test › debugging
design debugging
0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Electronic design automation › hardware verification and test
diagnosis
0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Electronic design automation › hardware verification and test
formal verification
0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Electronic design automation
hardware verification and test
0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Performance modeling and evaluation › simulation › analog and hybrid computer simulation
hybrid simulation
0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Computational complexity
boolean function analysis
0.011992
On the OBDD-Representation of General Boolean Functions · IEEE Trans. Computers 1992
Electronic design automation
hardware description language
0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Electronic design automation › hardware description language
VHDL
0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989

Methods — techniques the papers use, named apart from their topics

combinatorial analysis · 0.0symbolic execution · 0.0micro-probing · 0.0
YearPublicationVenuePosition
2014 Obfuscation for object-oriented programs: dismantling instance methods
abstract
Code obfuscation can help software developers protect technological secrets. Code readability is greatly enhanced with object-oriented technology that represents dynamic binding using instance method invocation. Therefore, dismantling instance methods is proposed in this paper as a critical obfuscating technique for object-oriented programs. The interception classes are interpolated first into the project. The static images and the up forwarders are then created. For each virtual function system and each interface function system, a respective dispatching function is set up. By properly arranging the class identifiers and binding identifiers, the switch statement in the dispatching function can be compiled into constant-time low-level code. After using dispatching functions to simulate virtual function system or interface function system invocations, all original instance methods in the project will be removed. Interception functions and export functions are indispensable in supporting the operation of callback methods. A prototype of our obfuscation system was implemented and successfully tested on some practical scale applications. Copyright © 2013 John Wiley & Sons, Ltd.
Heh-Tyan Liaw, Shih-Chieh Wei
Softw. Pract. Exp.1
1992 On the OBDD-Representation of General Boolean Functions
abstract
The behavior of ordered binary decision diagrams (OBDD) for general Boolean functions is studied. A tight upper bound of (2/sup n//n)(2+ epsilon ) for the worst case OBDD size is derived. Although the size of an OBDD is dependent on the ordering of decision variables, it is shown that almost all functions are not sensitive to variable ordering.>
Heh-Tyan Liaw, Chen-Shang Lin
IEEE Trans. Computers1
1990 Efficient Automatic Diagnosis of Digital Circuits
abstract
The problem of automatic diagnosis of digital circuits with efficiency is studied. Two improvements over the method of J.C. Madre et al. (1989) are developed to enhance the efficiency of diagnosis. Specifically, the dominance relation in circuit topology is utilized to reduce the search space of possibly correctable gates. In the authors' experiment, the search space is reduced to about one-half. A novel divide-and-conquer technique to determine the correct gate function is proposed.>
Heh-Tyan Liaw, Jia-Horng Tsaih, Chen-Shang Lin
ICCAD1
1989 VVDS: A Verification/Diagnosis System for VHDL
abstract
In this paper, an interactive verification and diagnosis system for VHDL [Vm88], VVDS, is presented. In VVDS, hybrid simulation, which simulates with both numerical and symbolic data, is implemented to achieve an effective compromise of the enormous quantity of input test data in the conventional simulation and the complexity of symbolic expression in the symbolic execution. To support efficient user interface in the verification and diagnosis process, both on-line programming of commands and micro-probing capability to passively and actively probe any level of design hierarchy are provided.
Heh-Tyan Liaw, K.-T. Tran, Chen-Shang Lin
DAC1