For more than two decades, the key objective for synthesis of linear decompressors has been maximizing encoding efficiency. For combinational decompressors, encoding satisfiability is dynamically checked for each specified care bit. By contrast, for sequential linear decompressors (e.g. PRPGs), encoding is performed for each test cube; the resultant static encoding considers that a test cube is encodable only if all of its care bits are encodable. The paper introduces a new class of sequential linear decompressors that provides a trade-off between the computational complexity and the encoding efficiency of linear encoding. As a result, it becomes feasible to dynamically encode care bits before a test cube has been completed, and derive decompressor-implied scan cell values during test generation. The resultant dynamic encoding enables an identification of encoding conflicts during branch-and-bound search and a reduction of search space for dynamic compaction. Experimental results demonstrate that dynamic encoding consistently outperforms static encoding in a wide range of compression ratios.

In this paper, a new linear decompress or is presented. A specific two-step encoding is incorporated in the implication process to exploit the degree of freedom during ATPG. The proposed decompress or achieves on average 247X test application time reduction for 10 industrial cores. A comparison with multiple seeds per pattern shows that the proposed decompress or achieves higher test application time reduction with fewer test patterns for 7 out of 10 industrial cores.

We present a shared memory based parallel diagnostic system to increase the throughput of volume diagnosis. The scheme takes advantage of copy-on-write (COW) to increase parallelization with given computational resources. The proposed method has no impact on diagnostic quality and it is applicable as addition to well-known partition based methods.

This paper presents a new X-blocking system which allows very high compression and full coverage even if the density of unknown values is very high and varies every shift. Despite the presence of Xs in scan cells, compression can be maximized by using PRPG and MISR structures. Results on industrial designs with various X densities demonstrate consistently high compression and full test coverage.

In this paper, a procedure for constructing time compactors based on a new 3-dimensional augmented product code is presented. Accordingly, augmented time compactors are constructed by assigning a unique tripletto each scan chain and calculating at least four sets of parity check bits. Each set of parity check bits is attached to one or more multi-input shift registers (MISRs). The proposed procedure allows an efficient construction for different classes of time compactors as well optimization and comparison of their properties. The constructed augmented time compactors demonstrate an ability to achieve a much higher compaction ratio than convolutional and modular compactors.

In this paper, a new space compactor, called an augmented multimode compactor, is presented. Accordingly, scan chains are separated into groups using t orthogonal partitions. The augmented multimode compactor has three modes such that all scan chains, a group of scan chains and an intersection of two groups of scan chains is selected for compression. Respectively, 1, kt-1 and any number of unknown states per shift-out cycle can be tolerated in these modes where k is the number of the compactor outputs assigned for observation of each scan chain. Simulation results demonstrate the efficiency of the proposed principles for constructing fully X-tolerant compactors. In the range of 0 to 10 percent of unknown states in test responses, the proposed scheme achieved the same or up to 3 times better observability than the fully X-tolerant combinational compactor.

Scan is widely accepted as the basis for reducing test cost and improving quality, however its effectiveness is compromised by increasingly complex designs and fault models that can result in high scan data volume and application time. The authors present a scan compression method designed for minimal impact in all aspects: area overhead, timing, and design flow. Easily adopted on top of existing scan designs, the method is fully integrated in the scan synthesis and test generation flows. Data and test time compressions of over 10times were obtained on industrial designs with negligible overhead and no impact on schedule.

Scan-based tests created by automatic test pattern generators (ATPG) can be efficiently compressed and applied in a deterministic built-in self-test (DBIST) architecture. However, the BIST environment adds significant complexity to failure diagnosis. We present a simple scan-compatible diagnosis solution - streaming DBIST (SDBIST), which is based on a low-overhead hierarchical compactor SDBIST allows continuously monitoring streaming scanout data for reduced-volume expect-data diagnosis, on-line fail-data collection and selective scan cell masking.

Complex SOC's developed in VDSM technologies require adequate solutions to diagnose and analyze yield losses. This paper focuses on the diagnosis of logic circuits embedded in SOCs. The core instrument leveraged is ATPG used during test vectors generation and analysis of failures. This work emphasizes the results obtained in systematically applying ATPG diagnosis on failures detected in the manufacturing test floor. Details on diagnosis flow and ATE data collection are given. Experimental results are provided.

This paper extends the reconfigurable shared scan-in architecture (RSSA) to provide additional ability to change values on the scan configuration signals (scan enable signals) during the scan operation on a per-shift basis. We show that the extra flexibility of reconfiguring the scan chains every shift cycle reduces the number of different configurations required by RSSA while keeping test coverage the same. In addition a simpler analysis can be used to construct the scan chains. This is the first paper of its kind that treats the scan enable signal as a test data signal during the scan operation of a test pattern. Results are presented on some ISCAS as well as industrial circuits.

In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.

In this paper, we present a technique for reducing the test length of counter-based pseudo-exhaustive built-in self-testing (BIST) using a width compression method and a divide-and-conquer strategy. More formally, the target faults are divided into K groups such that a binary counter can generate a test set for each group. By selecting the size of the binary counter, this technique allows a trade-off between test application time and area overhead. The experimental results for the ISCAS'85 and ISCAS'89 benchmark circuits demonstrate the efficiency of the proposed technique. In all cases, this low-overhead BIST technique achieves complete fault coverage of the stuck-at faults in reasonable test application time.

In this paper, an efficient test pattern generation (TPG) algorithm for combinational circuits based on the Boolean satisfiability method (SAT) is presented. The authors propose a new data structure for the complete implication graph that increases the precision of implication process. Next, they examine approaches like a single-cone processing, single path-oriented propagation, and backward justification and show that they are efficient to improve robustness of TPG algorithms. Finally, the authors propose efficient techniques and heuristics for these approaches. The resultant automatic test pattern generation system, called SPIRIT (Satisfiability Problem Implementation for Redundancy Identification and Test generation), combines the flexibility of the SAT-based TPG algorithms with the efficiency of the structural TPG algorithms. Experimental results demonstrate the robustness of the proposed TPG algorithm. Without fault simulation, SPIRIT is able to achieve 100% fault efficiency for a large set of benchmark circuits in a reasonable amount of time.

In this paper, we present a new data structure for a complete implication graph and two techniques for low complexity static learning. We show that using static indirect &Lgr-implications and super gate extraction some hard-to-detect static and dynamic indirect implications are easily derived during static and dynamic learning as well as branch and bound search. Experimental results demonstrated the effectiveness of the proposed data structure and learning techniques.

In this paper we present a robust test generation algorithm for combinational circuits based on the Boolean satisfiability method called SPIRIT. We elaborate some well-known techniques as well as presenting new techniques that improve the performance and robustness of test generation algorithms. As a result, SPIRIT achieves 100% fault efficiency for a full scan version of the ITC'99 benchmark circuits in a reasonable amount of time.

In this paper an efficient test pattern generation (TPG) algorithm for combinational circuits based on the Boolean satisfiability method (SAT) is presented. We examine some not so popular approaches as a single cone processing, single path oriented propagation and backward justification. We give a new definition for SAT-based test generation and present duality of learning phenomenon. The resultant ATPG system, called SPIRIT, combines the flexibility of SAT-based TPG algorithms with the efficiency of structural TPG algorithms. Experimental results demonstrate the efficiency and robustness of the proposed TPG algorithm. Without fault simulation, SPIRIT is able to generate complete test sets for the ISCAS'85 benchmark circuits and full scan version of the ISCAS'89 benchmark circuits within 3 minutes on a 450 MHz Pentium-III PC.

We show that the test generation problem for all single stuck-at-faults in sequential circuits with internally balanced structures is reduced into the test generation problem for single stuck-at-faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at-faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at-faults on separable primary inputs.