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Suhas S. Patil

dblp:57/262 · DBLP profile ↗
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4ranked-venue papers
2as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-authorComputer networks · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 65% Integrated circuit design · 35%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design › logic array
storage/logic array		 0.021979
A Programmable Logic Approach for VLSI · IEEE Trans. Computers 1979
An Approach to Using VLSI in Digital Systems · ISCA 1978
Electronic design automation
physical design		 0.011981
ABLE: A LISP-based layout modeling language with user-definable procedural models for storage/logic array design · DAC 1981
Electronic design automation › logic synthesis
programmable logic array		 0.011979
A Programmable Logic Approach for VLSI · IEEE Trans. Computers 1979
Electronic design automation › design methodology
hardware design methodology		 0.011978
An Approach to Using VLSI in Digital Systems · ISCA 1978
Electronic design automation › design methodology
VLSI design methodology		 0.011978
An Approach to Using VLSI in Digital Systems · ISCA 1978
Integrated circuit design
VLSI design		 0.011979
A Programmable Logic Approach for VLSI · IEEE Trans. Computers 1979

Methods — techniques the papers use, named apart from their topics

LISP-based procedural models · 0.0programmable logic design · 0.0
YearPublicationVenuePosition
2023 An optimization-driven model for a hybrid beam forming for massive multiple-input multiple-output
Minal K. Pawar, Suhas S. Patil
 Wirel. Networks2
1981 ABLE: A LISP-based layout modeling language with user-definable procedural models for storage/logic array design
Gary B. Goates, Suhas S. Patil
 DAC2
1979 A Programmable Logic Approach for VLSI
abstract
This paper explores the use of a proposed programmable storage/logic array (SLA) chip as a general purpose universal logic element for digital computers. The SLA is compared to other programmable logic arrays in implementation and utilization, showing how it permits construction of complete digital subsystems on one chip without sacrifice in programmability. When compared with other contending very large-scale integrated technology (VLSI) approaches, such as microprogrammed processors and gate arrays, the SLA offers an attractive combination of cost, performance, and ease of implementation.
Suhas S. Patil, Terry A. Welch
 IEEE Trans. Computers1
1978 An Approach to Using VLSI in Digital Systems
abstract
We explore the use of a proposed general purpose programmable Storage/Logic Array chip (SLA) as a universal logic element for digital computers. Design examples are given to show how SLAs could be used in computer design. This approach to VLSI is compared and contrasted with other contending approaches using microprocessors, gate arrays and customized VLSI chips. The SLA appears attractive because of low cost, reasonable high performance and shorter implementation time.
Suhas S. Patil, Terry A. Welch
 ISCA1