VLDB 2026 Research / reviewers in the wild / expert
H. Daniel Schnurmann
dblp:57/2621
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1975
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 89% Performance modeling and evaluation · 11% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 1 | 1975 | The Weighted Random Test-Pattern Generator · IEEE Trans. Computers 1975 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1975 | The Weighted Random Test-Pattern Generator · IEEE Trans. Computers 1975 |
Electronic design automation › hardware verification and test › random testing
weighted random pattern testing |
0.0 | 1 | 1975 | The Weighted Random Test-Pattern Generator · IEEE Trans. Computers 1975 |
Performance modeling and evaluation
delay analysis |
0.0 | 1 | 1969 | A Statistical Approach to the Computation of Delays in Logic Circuits · IEEE Trans. Computers 1969 |
Electronic design automation
timing analysis |
0.0 | 1 | 1969 | A Statistical Approach to the Computation of Delays in Logic Circuits · IEEE Trans. Computers 1969 |
Methods — techniques the papers use, named apart from their topics
statistical random sequence generation · 0.0heuristic weighting · 0.0multiple regression · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1975 | The Weighted Random Test-Pattern GeneratorabstractA heuristic method for generating large-scale integration (LSI) test patterns is described. In particular, this paper presents a technique for generating statistically random sequences to test complex logic circuits. The algorithms used to obtain a set of tests by means of weighted logic signal variations are included. Several techniques for assigning these weights and for varying them are discussed on the basis of the primary algorithm. Also described is a means of obtaining a minimal number of test patterns. This approach has proved successful in obtaining fault-detecting patterns. H. Daniel Schnurmann, Eric Lindbloom, Robert G. Carpenter |
IEEE Trans. Computers | 1 |
| 1969 | A Statistical Approach to the Computation of Delays in Logic CircuitsabstractThis paper describes a method whereby multiple regression techniques are used to predict the delay between input and output signals through a combinatorial logic chain. H. Daniel Schnurmann, Klim Maling |
IEEE Trans. Computers | 1 |