Stringent quality requirements for safety-critical applications drive the demand for "zero defects" in modern ICs. In this context, delay characterization of standard cells for resistive open defects is an increasing concern due to aggressive timing margins in digital circuits. The problem is made worse by the large number of open defect sites in standard cells, combined with a wide range of defect resistance values for each site. This incurs possible prohibitive costs for defect simulation and characterization. To alleviate this complexity, we propose Resistive Fault Dominance (RFD) for resistive open defects. RFD eliminates simulations of certain open defects with intermediate defect resistance values that are guaranteed to exceed specified timing margins for standard cells, based on tests for specific "dominant" open defects. This can significantly reduce the computational costs of cell library characterization and simulation effort by 84%-91%. An algorithmic fault simulation methodology for resistive open defects on parasitic-extracted (PEX) transistor-level netlist is developed.

Nowadays, AI applications are becoming extremely popular in our everyday life as well as for the industry. Recent incidents involving hyperscalers have revealed that even cloud-based datacenter hardware can experience failures leading to Silent Data Corruptions (SDCs), also called Silent Data Errors (SDEs). This Special Session delves into the implications of such failures on AI workloads, both during training and inference, and explores methodologies for efficiently detecting SDCs or SDEs through dedicated monitoring phases.

Functional state extraction of both sequential logic and arrays in a design is widely used in the industry to debug logic and timing bugs. Typically, this is done by repurposing logic and array test DFT that is already present in the design. In this paper, we describe the logic state extraction methodology as practiced in Intel servers, which is referred to as "scan dump". First, we motivate the state extraction problem and provide contextual background. Secondly, we describe design-for-test (DFT) implementation in support of scan dump for state extraction. Thirdly, we describe the pre-silicon validaion methodology for scan dump. Fourthly, we describe a set of best practices for implementing the scan dump feature. Finally, we describe an actual debug example using scan dump.

IEEE 1687, also known as iJTAG, was published late in 2014. Following IEEE policy, a standard need to be revisited and potentially refreshed at least every 10 years. For IEEE 1687, this refresh is not only ongoing, but close to completion. In this presentation, we will go over some of the key updates and upgrades, as well as an outlook on the remaining process to get the refreshed standard published.

Intel uses AI across the entire product life cycle, from design to product ship. In this talk, the speaker will discuss applications of AI for product development that spans post Si work and test manufacturing flows. The talk will focus on traditional ML applications in Intel’s test manufacturing flow that combine ML techniques and innovation in test infrastructure development to deliver personalized unit testing for optimizing test cost, product performance and improving outgoing quality. He will also go over how Intel is deploying generative AI for product development work to accelerate time to market while improving quality.

For large scale data center fleets, a single Silent Data Error (SDE) event leading to computational inaccuracies has the potential to be disruptive to their end users especially when mission critical workloads are being run. With large deployments of machines in the data center, SDE rates as low as 10FIT can be detected. At the same time, silicon die area and core count in an SOC is continuing to increase with advanced packaging technologies further making it challenging. Intel has developed DCDiag tool that has a suite of diverse tests that rely on pseudo-random data and instruction combinations to detect data miscompute. These tests can be studied empirically to develop optimization methods to identify test content for effectively detecting SDEs at CPU manufacturing flow, ODM screening flow and infield fleets. While optimizing screening content is key and could be different across product generations, detecting SDEs is challenging since many of the data miscompare errors are dependent on a combination of conditions that may exist during an error. This leads to poor repeatability of DCDiag tests to capture the SDE fails which demands long test times and/or resiliency methods to minimize impact. This presentation outlines the challenges for SDE detection from CPU manufacturing to Data Center fleets and the why the notion of resilience in HW and SW is critical in data centers.

Stress test is a common practice in the industry for accelerating latent defects and to pull in early life failures. Stress test requires voltage and temperature elevation for screening latent defects. This in turn implies that static timing analysis (STA) needs to be done at elevated voltage and temperature conditions. Timing closure at elevated voltages increases design area, power dissipation, and timing convergence effort. We present a relaxed timing closure methodology that targets timing closure in select DFT logic. Secondly, to ensure that the required switching activity needed for stress is achieved in the design, a specialized toggle monitor circuit is introduced. The toggle monitor can check for sign-of-life during stress test. Use of toggle monitor and relaxed timing closure on select DFT logic mitigates the design impact of timing closure at elevated voltages. Finally, it is observed on silicon that the stress content is applied correctly.

A logic diagnosis procedure produces a set of can-didate faults that are expected to identify the defects present in a faulty chip. To reduce the number of candidates produced, diagnostic tests are often needed. The use of diagnostic tests increases the storage requirements of a test set. Earlier works reduced the input storage requirements of a fault detection test set by using each stored test to apply several different tests. When applied to diagnostic tests, the tests were selected by performing diagnostic fault simulation of a basic fault model. In this paper, we apply this approach to target large sets of candidate faults produced by a logic diagnosis tool. A procedure for the selection of a subset of the available tests to be used as diagnostic tests is described. Experimental results for simulated defects in benchmark circuits and the logic blocks of an OpenSPARC T1 microprocessor show that the diagnostic test set selected using our approach produces better diagnosis results, with a minimal increase in input storage, compared to a diagnostic test set produced by a commercial tool.

With increase in functionality expected of a chip, it is becoming increasingly difficult to contain the entire logic in a single die. This is because higher die area leads to lower yield, and therefore to improve yield, die disaggregation is gradually becoming a standard practice across the industry. Additionally, not all functionality requires a leading-edge process technology, so different functionality can be partitioned across heterogenous dies. This has led to packages with multiple heterogenous dies. In this work, we describe a test fabric that is scalable across multiple dies. First, we describe different components of a scalable test fabric architecture. Second, we describe how pattern sets for a die can be re-used in different package configurations of which the die is a component. Third, we describe test generation methodology for disaggregated dies with identical logic blocks.

Abhishek Basak (Nvidia)

Sankaran Menon (Intel), Eric Rentschler (Siemens EDA), Ilya Wagner (Intel), Spencer Millican (Auburn University)

The goal of speed path validation is to identify frequency limiting paths in a fabricated IC. It is a complex and expensive activity, requiring significant manual expertise. This paper provides a tutorial overview of speed path validation, focusing primarily on the state of the practice and its limitations. This paper also discusses delay test and discusses synergies between the two disciplines.

Achieving high yield in deep-submicron technologies is challenging due to the presence of unforeseen defect mechanisms, requiring increases in test complexity and efficiency. We focus on shorts within standard cells which are traditionally targeted by DC tests. Recent research has shown the need for multi-pattern tests where intermediate defect resistance values are concerned, as opposed to extreme values considered by prevalent test techniques. In this research, we show that there exist ranges of short defect resistance values that escape traditional DC tests while incurring unexpectedly large delay values for specific two-pattern stimuli. It is seen that these resistance values are approximately in the range of defect resistance values observed for realistic short defects in industry. These defects must therefore be prioritized from a circuit level critical path delay testing perspective to minimize overall circuit DPPM. Such catastrophic increase in delay is due to the fact that specific shorts in standard cells influence the delays of logic gates feeding into and out of the standard cell, resulting in path delay increase of 50X-SOX with respect to the delay of a single cell. Two-pattern tests are derived for such faults and simulation results on standard cell designs and ripple carry adders are presented to further our arguments.

Recent advances in process technology have resulted in novel defect mechanisms making the test generation process very challenging. In addition to complete opens and shorts that can be represented via extreme defect resistance magnitudes, partial resistive opens and shorts are also of concern in deeply scaled CMOS technologies. For open defects with intermediate defect magnitude values, it has been shown that multi-pattern tests are necessary for defect exposure. We extend this approach to short defects with intermediate defect magnitude values to obtain a suite of multi-pattern tests for standard cell instances that cover complete as well as partial intra-cell open and short defects. A hierarchical scan-compatible SAT-based test generation approach for full scan sequential circuits is then proposed that allows such multi-pattern tests to be applied to the circuit via the scan infrastructure. A key innovation is the combined use of shift and capture operations along with launch-on-capture and launch-on-shift scan based test application for increased defect coverage. Resulting defect coverage improvements over conventional two-pattern tests are demonstrated on ISCAS89 benchmark circuits.

As integrated circuit manufacturing advances, the occurrence of systematic defects is expected to be prominent. A methodology for predicting potential systematic defects based on design-for-manufacturability (DFM) guidelines was described earlier. In this paper we first report that, among the faults obtained based on DFM guidelines, there are undetectable faults, and these faults cluster in certain areas of the circuit. Because faults may not perfectly represent potential defect behaviors, defects may be detectable even though the faults that model them are undetectable. Clusters of undetectable faults thus leave areas in the circuit uncovered for potential systematic defects. As the potential defects are systematic, the test escapes can impact the DPPM significantly, and thus lead to circuit malfunction and/or reliability problems after deployment. To address this issue in the context of cell-based design, we propose a logic resynthesis procedure followed by physical design to eliminate large clusters of undetectable faults related to DFM guidelines. The resynthesized circuit maintains design constraints of critical path delay, power consumption and die area. The resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that both the reduction in the numbers of undetectable faults and the reduction in the sizes of undetectable fault clusters are significant.

Ensuring high defect coverage for advanced CMOS technology nodes has been a major challenge for the IC test industry. Traditional test methods using fault models such as stuck-at and transition faults with a primitive gate-level abstraction of design netlists have been shown to be inadequate for detecting open-circuit and short-circuit defects within instances of standard cells used in those netlists. Recent advances in Cell-Aware Test (CAT) using single pattern and two pattern tests have demonstrated increased coverage of such defects in industrial IC designs. However, the simulation overhead of defect characterization for all the cells in a library practically limits the size of defects that are explored to large magnitudes. Furthermore, certain effects such as charge sharing within cells can necessitate tests that span more than two time frames to expose subtle defects. This work, through simulation, identifies defects of certain sizes that can go undetected by current methods. It then proposes an algorithmic approach towards cell characterization that can result in faster identification of cell input stimuli vis-a-vis a defect simulation based method.

We describe a novel methodology to validate path level static timing analysis (STA) on silicon by leveraging standard scan architecture and using hazard-free robust path delay tests. We have successfully validated a sizable set of timing paths on silicon across multiple advanced process nodes. Learnings from these STA correlation exercises on representative ASIC blocks in test chips have resulted in a silicon-proven STA signoff methodology with optimum guard-bands. The process health feedback has proved valuable for the process development team especially during the early development phase. We have observed that Fmax determined using hazard-free robust path tests is within ±5% of that using functional benchmark.

Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Layout features that result in DFM guideline violations may not be avoided completely due to the design constraints of chip area, performance, and power consumption. A framework for translating DFM guideline violations into potential systematic defects, and faults, was described earlier. In a cell-based design, the translated faults may be internal or external to cells. In this article, we focus on undetectable faults that are external to cells. Using a resynthesis procedure that makes fine changes to the layout while maintaining the design constraints, we target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable. By eliminating the corresponding DFM guideline violations, we ensure that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field. The layout resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that the improvement in the coverage of potential systematic defects is significant.

Yield improvement, yield ramp, and defect screening have been major areas of concern for the semiconductor industry as technology nodes have advanced. Much effort has been focused on capturing the defects missed by traditional stuck-at and transition delay fault model based testing. A majority of these un-modeled defects stems from features inside a standard cell or between two adjacent standard cells. Traditionally, critical area has been used as the manufacturability guideline to determine opens and shorts that should be targeted for test. This paper motivates a new paradigm - a design-for-manufacturability (DFM) hotspot-aware fault model to target intra-cell and inter-cell defects. The basic objective behind this approach is to bring in knowledge of manufacturing vulnerability in design layouts to weigh likelihood of occurrence of systematic defects. Recent technologies have standard cells much smaller than the lithography-driven optical diameter which means the cell's feature context is a key driver for DFM-driven fault sensitivity. This paper describes a novel automated flow for cell characterization that can be used to create patterns at the cell boundary for DFM-aware faults. The paper presents ATPG results for different DFM-aware faults, and analyzes the coverage gaps. Finally, the paper ends with a comparison with the cell-aware and dual-cell-aware fault models, and describes relative advantages and application scenarios.

Start of the above-titled section of the conference proceedings record.

We describe a procedure based on an existing static timing analysis tool for selecting path delay faults to target during test generation. The use of an existing static timing analysis tool ensures that a state-of-the-art process can be used for estimating path delays. However, static timing analysis, by itself, can be inaccurate as it does not take into consideration conditions that are necessary for detecting path delay faults. In the proposed method, these conditions are captured as what are called input necessary assignments, which static timing analysis tools are able to use. By providing the static timing analysis process with the input necessary assignments for a selected path, the static timing analysis process can estimate the delay of the path more accurately. It can also identify additional paths whose delays are at least as high as those of the selected paths. Thus, feeding back the input necessary assignments to the static timing analysis process enhances the correlation between static timing analysis and actual timing of tests on silicon. The result is a set of potentially detectable path delay faults associated with critical paths based on more accurate estimates of the path delays that can be exhibited by a test set, compared with the set that would be obtained by static timing analysis alone.

The impact of di/dt noise and static IR drop on at-speed scan testing has been reported in literature. Delays of paths can be impacted during delay testing by IR drop and di/dt noise in ways that change the delay ordering of paths. This, in turn, affects the ability of such tests to catch certain delay defects and impairs its use for speed binning. It is important, therefore, to address IR drop during delay tests. This paper proposes an instrumentation methodology for a design based on launch-off-capture delay tests to control the time interval between shift and capture cycles. This mechanism improves speed characterization of devices and achieves a higher capture frequency compared with traditional methods. It also addresses reduction of di/dt noise during capture. The proposed scheme is realized by (i) pipelined scan-enable and (ii) a deterministic launch-and-capture method for the tile under test. This mechanism has been implemented on silicon and experimentally observed to increase the speed of a device between 8% and 24% relative to traditional methods.

Summary form only given. In the industry today, testing packaged chips achieves the outgoing DPPM (defective parts per million) requirements. Usually, functional and structural test patterns are used at wafer sort, followed by functional/structural testing with packaged parts, and then by functional system level testing, each subsequent stage significantly more expensive than the previous one. By and large, wafer test have not been used for performance binning and reliability screening. Also, packaged parts are tested in burn-in chambers and on load boards, using either the same structural patterns used at wafer sort or with functional test patterns. As design complexity has gone up significantly over the past decade, the test cost has grown disproportionately. If a die is found to be faulty at a stage after wafer sort, then the design house incurs the cost of packaging, and for subsequent testing. In one business model, the fabless design house buys dies from the foundry that pass wafer sort, and needlessly pays for dies that are later found to be bad after packaging. Furthermore, this problem can be severe for dies that go into multi-chip modules or stacked ICs, as all the dies in the packaged chip have to be thrown away even if one constituent die is found to be bad. Since it is increasingly more expensive to test chips down-stream (using functional testers or on a system) and since there is downward pressure on product costs with the advent of inexpensive SoCs, it becomes important to achieve maximum test quality in terms of defectivity and binning, at wafer sort. Known good die (KGD) refers to dies which have been tested to the same quality and reliability levels as their packaged counterparts. Even though the KGD problem has been discussed since the mid 90's, the problem becomes more and more difficult with every new process node and new design requirement. There is need to develop high quality tests, on die DFX instrumentation, and reliability screens that can be applied at wafer sort, given pin constraints. In addition to addressing failure mechanisms of a bare die, such as gross defects, small delay defects, cross-talk, and variations due to photolithography, a good wafer sort test methodology and associated tests should not only be enough to reject bad bare dies, but also characterize the dies enough to enable estimation of the performance/power of packaged parts on a system.

Today's electronic systems and those envisioned for the near future exploit significant integration of devices on a chip with incredibly shrinking device/interconnect geometries. Such systems operate very close to their power/performance margins to achieve maximum profitability. The increase in the design complexity of such systems that now include digital and analog components, coupled with the race to reach the market faster severely constrains the resources and time to validate and test them. Furthermore, products can also fail to operate correctly in the field prior to their expected end-of-life due to transient errors or aging.

With the advent of ultra large scale integration on silicon, computing and communication devices are trending towards a system-on-chip (SoC) on a single die integrating several processor cores, several types of high-speed I/O interfaces and analog components. The integration of such diverse components along with associated loss of controllability and/or observability of each component is already creating significant issues for reliable test of such chips.

Capacitive crosstalk can slowdown transitions which can propagate to outputs and cause erroneous operation. Test generation methods such as XGEN and XGEN-E were proposed to generate tests for such failures. However, a drawback of these test generation methods is that a large proportion of faults are aborted. In this paper, we systematically derive a multi-valued algebra. We first show that a composite value system must be derived considering all operations performed by the algorithm that will use the value system. In particular, we identify that for our test generation algorithm it is imperative to consider its timing operations and their impact on what composite values can exist in our algebra. We also identify the fact that even some key procedures - namely the backtrace procedure as well as the search procedure - need to be modified to work with the composite value system. We derive a new 57-valued algebra and modify the key ATPG procedures to obtain a test generation methodology which we call XGEN-M ('M' for multi-valued). We present experimental results that demonstrate the superiority of XGEN-M compared to previous methods.

Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error A test generation methodology, called XGEN, was developed to generate tests for such failures. Two drawbacks of XGEN are: (i) it is not complete because of restricted propagation conditions, and (ii) a constrained logic value system is used. In this paper, we relax the propagation conditions to increase the solution space. This increases the likelihood of finding a test. We also present a nine-valued algebra that distinguishes between hazardous values and non-hazardous values. Finally, we use the relation between arrival time and required time ranges to selectively turn off the timing computation procedure which is computationally expensive. Other drawbacks of previous versions of XGEN are: (i) a simplified pin-to-pin delay model was used, and (ii) crosstalk computation could not handle timing ranges. We have addressed both of those issues.

Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show that in 0.13 /spl mu/m technology such noise in local interconnects embedded in combinational logic can exceed the threshold voltage. We show the impact of such noise on different kinds of circuits. The magnitude of this noise can increase due to process variations. We present an algorithm for generating vectors for validation and manufacturing test to detect logic-value errors caused by inductance induced oscillation. To facilitate the vector generation method, we have derived analytical expressions, as functions of rise and fall times for (i) the magnitude of overshoots and undershoots, and (ii) the settling time, i.e., the time required for the circuit response to settle to a bound close to the final value.