With the rapid development of the techniques of semiconductors, Internet of Everything (IoE), industry 4.0 and smart power are going to be realized, agile and accurate edge detection on pulse signals becomes essential for supporting versatile sensing applications targeting ubiquitous IoE monitoring. To ensure accurate pulse signal sensing at the edge with low power, a novel silicon-integrated mixer-enabled adaptive sensing platform is proposed. Based on the innovative chip architecture composed of the low-power ring voltage-controlled oscillator (VCO) and current-bleeding mixer on-chip, the wideband pulse signal would be mixed with the sinusoidal LO signal generated by VCO and detected by low-pass filtering and further digital processing. The frequency of the VCO can be configured flexibly by the FPGA to cover different pulse detection scenarios. Moreover, the VGA and the LPF are flexibly configurable to meet the link budget requirements and ensure accurate and adaptable detection covering various scenarios. Based on the systematic theoretical evaluation of the novel flexible sensing chip architecture, target pulse signals can be detected, exploring the capability of the efficient chip-based edge pulse detection system to be deployed for applications such as sustainable partial discharge detection for power electronics monitoring, ultrasound sensing, and so on.

A novel mixed-signal adaptable silicon-based coherent photoacoustic (PA) sensing system-on-chip (SoC) is proposed to detect various kinds of target signals robustly under high noise and strong interferences in compact chip-level, attaining precise in vivo sensing for physiological signs monitoring and enhanced bio-imaging. Based on the configurable coherent PA sensing SoC architecture supported by on-chip Gilbert cell-based multiplier, a digital processing module, and DACs, in-phase (I) and quadrature (Q) templates generated by digital module on-chip are configurable to be with a high correlation coefficient to the target PA signal, attaining detection and reconstruction of target signals in a coherent detection mode. The correlation between the received PA signal and the templates is implemented efficiently, assuring accurate tracking and precise reconstruction on the target PA signals at the chip level. Based on the integrated PA SoC fabricated by the TSMC 65-nm CMOS process, precise in vivo sensing and imaging can be assured at the edge. Further, as PA detection leverages optical and ultrasound sensing, in vivo imaging on in-depth vessels or other tissues can be attained. The mixed-signal PA SoC paves the way for sustainable health monitoring and owns immense potential for early disease diagnostics based on in vivo blood temperature sensing and vessel imaging.

A 12th-order active-RC bandpass filter (BPF) for a synthetic aperture radar (SAR) receiver is presented in this paper. The proposed BPF is composed of six cascaded Biquads and each Biquad is configured as a second-order bandpass stage and the switched resistor and capacitor arrays are used in the Biquad to enable the digital control of the passband center frequency and bandwidth. To achieve desired passband and behave with Chebyshev response, the capacitors in the six Biquads are designed with the same values and resistor values are tunable. The filter has been implemented in a 65 nm CMOS technology and achieved low ripple, low noise and low power consumption. Under 8-bit digital programmable, the center frequency is tunable from 0.98 MHz to 4.83 MHz and the bandwidth is tunable from 0.66 MHz to 5 MHz, and it measures a maximum in-band frequency response deviation of <0.6dB while consuming $\leq$12mW at a 1.2 V supply.

With the rapid development of the internet of things (IoT), industry 4.0, smart manufacturing, intelligent building techniques, robots are becoming more and more demanding for emerging new applications. For robots used in complex environments, precise sensing of its surroundings is essential to enable safe and robust operation. Comprehensive and cognitive perception capability is needed to recognize human subjects in a complex and dynamic environment to avoid the possible collisions. Moreover, comprehensive sensing is required to enable accurate simultaneous localization and mapping (SLAM) under scenarios with clutters and moving human subjects. To achieve the goal, a CMOS-integrated radarassisted robot sensing platform is proposed. By leveraging the phased-array radar techniques and time-phase processing techniques, high accuracy can be achieved for localization and recognition of human subjects. Fabricated in a 65-nm CMOS process, the chip-scale radar sensing platform is with compact size. A series of experiments have been carried out on verifying the capabilities of the radar platform for ranging and human recognition based on vital signs, exploring the potential for seamless human-robot interaction applications.

A 1GHz configurable chirp modulation (CM) direct digital frequency synthesizer (DDFS) is presented and implemented in 65nm CMOS technology. This DDFS is designed to generate 70-86MHz chirp signal for X-band frequency modulated continuous wave (FMCW) radar system. The proposed design is composed of 64-bit frequency control word (FCW) serial peripheral interface bus (SPI) supported 20-bit frequency/phase accumulator and 10-bit linear/non-linear hybrid digital-to-analog convertor (DAC). This DDFS supports saw-tooth chirp mode and exhibits 20-900 μs time of chirp duration (TCD) and 1ms pulse recurrence frequency (PRF), dissipates 24mW@1GHz clock from a 1.2V supply. The DDFS core occupies 180μm×170μm area.

An ultra-lower power (ULP) MEMS-based FSK transmitter is implemented in 65 nm CMOS. The transmitter operates in ISM-915 MHz band using a binary FSK modulator employing the high-Q dual microelectromechanical system (MEMS) resonators. The transmitter using an adaptive fast switching binary FSK modulator generates FSK signals in 915 MHz band with -8.2 dBm output power, supporting up to 10 Mb/s data rate. The phase noise (PN) of the FSK modulator was measured for each of the two different operation frequencies, achieving -139.4dBc/Hz and -138.7dBc/Hz at a 1-MHz offset at 911.9 MHz and 923.1 MHz, respectively. At 10 Mb/s, the transmitter consumes 753 pW, which translates to energy-efficiency of 75.3 pJ/b.

To minimize the area of analog-to-digital converters (ADCs) for multichannel applications and break the SNDR limitation caused by DAC-induced nonlinearity, a more area-efficient mismatch error shaping (MES) scheme is proposed in noise shaping (NS) successive-approximation (SAR) ADC. By employing a switched-capacitor (SC) voltage divider, the proposed method makes the flash ADC and data weighted averaging (DWA) digital circuits in the original MES method obsolete. Therefore, the complexity of the architecture is highly reduced, and the area is significantly reduced to 0.037 mm2. In addition, the power consumption for the MES implementation is significantly decreased by more than 7.3%. The proposed SAR ADC is fabricated in GF 40-nm CMOS technology. The measurements show that the proposed MES technique improves the SFDR from 64 to 102 dB and decreases the THD from -63.6 to -95.7 dB. The SNR and SNDR in a 20-kHz bandwidth are 91.6 and 90.2 dB, respectively. The power consumption is 383.4 μW with a 1.1-V power supply at a 16-MS/s sampling rate.

For wearable biomedical devices, it is essential to detect target signals under high noise and strong interferences. Moreover, it is critical to realize the system with compact size and easy implementation. To address both goals, this paper presents a chip-based photoacoustic (PA) sensor called QuACL. By leveraging the adaptive coherent lock-in technique, the high sensitivity and specificity can be achieved for detecting target signals. In-phase and quadrature PA templates are specifically designed based on the profile of the target signal and are generated by the FPGA board and the DAC board. The received signal is correlated with the templates to capture, track, and recover the target PA signal. Fabricated in 65-nm CMOS technology, the chip-based sensor system occupies only 0.6 mm2area. The robustness and versatility of the QuACL sensor system are verified by the experiments on discerning and recovering weak PA signals accurately.

Flexible and wearable devices are emerging with the developing of the sensors and IoT (internet of the things). The power consumption and volume of such devices are dominant limitations for wearable feature in various applications. To meet the requirements, a photoacoustic receiver system-on-chip (SoC) is developed and fabricated with a novel correlation detection technique based on the early-and-late tracking. Through this method, output SNR of the receiver can be significantly improved. For this, a low power and high sensitivity analog front-end (AFE) with a noise shaping (NS) SAR ADC is implemented. As oversampling is necessary for the accurate delay of digital processing, noise shaping technique is implemented in the SAR ADC. Simulation results show that, the AFE achieves 70 dB dynamic range and 20 μV sensitivity for about 30 dB output SNR. The SAR ADC can obtain 71 dB SNDR under 50MSps sampling rate with the aid of the NS technique. Based on the analog circuits design, the digital part for the detecting technique is also implemented on chip. The whole power consumption is about 15 mW on the TSMC 65 nm CMOS process.

The paper presents a two-stage cascade push-pull power amplifier (PA) with floating-body transistors in 130 nm Silicon-On-Insulator (SOI) CMOS process for IEEE 802.11ac application. In the proposed design, on chip baluns, which can realize impedance matching, are used in driver stage amplifier input and power stage amplifier output matching networks. The proposed PA can achieve high gain, high output power and wide bandwidth at the same time with 0.819mm2chip area including pads. With 2.5 V supply voltage, the implemented PA achieves 20.31 dB power gain with 3 dB bandwidth range from 3.9 GHz to 6.19 GHz, 20.96 dBm output power at 1 dB compression point (OP-1dB) and 9.85% power added efficiency (PAE).

Diabetes mellitus is a prevalent metabolic disease which requires daily glucose monitoring for patients. Commercially available devices are all finger-prick which is painful and costly. Herein, we developed a portable and noninvasive glucose sensor based on photoacoustic (PA) technique. The size of the sensor main body is 17cm(L) × 14cm(W) × 10cm(H) with a weight of 650g (including a power bank). The system configuration is shown and the performance was evaluated by in vitro experiment on aqueous glucose solution at both high (1~8g/dL) and low concentrations (50~350 mg/dL). The R2and RMSE values achieved are 0.9526, 0.5903g/dL and 0.8966, 40.18mg/dL, respectively. Moreover, Clarke Error Grid analysis is also applied for physiological concentration prediction evaluation and 71.43% of data points fall in region A and the remaining points are in B, indicating the potential of our portable PA glucose sensor for clinical application.

Integrated frequency modulated continuous wave (FMCW) radar on chip (RoC) shows huge potential on real-time, versatile, wireless monitoring of human health conditions with low power, high sensitivity and compact size. This paper presents a Ku-band FMCW RoC working at 15 GHz center frequency, which can realize accurate continuous health monitoring based on interferometry phase analysis algorithm. A digital-tunable mixed-signal-mode FMCW chirp synthesizer is designed to ensure the phase accuracy with high power efficiency. A saturated driver-amplifier and power-amplifier chain is used to suppress the chirp ripples, thus ensuring the accurate phase measurement. Fabricated in 65 nm CMOS technology, the prototype demonstrates 1 GHz chirp bandwidth with 1.2 V supply and 238 mW power consumption, which satisfies the low-power requirement for continuous-time healthcare monitoring applications. Experiments on detecting various kinds of micro physiological signals are carried out using the FMCW radar chip prototype based on the phase analysis algorithm. The radar and the phase analysis algorithm can be further integrated into an ASIC to realize higher performance on healthcare monitoring.

In this paper, a delay locked loop (DLL) based configurable multi-phase clock generator with wide operating range and high resolution is proposed. It is implemented by adopting array of configurable DLLs and is able to generate multi-phase frequencies with true-time-delay, which is essential in a wideband FMCW phased array system. Fabricated in a 40nm CMOS process, the proposed multi-phase clock generator achieves configurable phase delay with high resolution of 7ps under varies of reference frequency from 400MHz to 2.5 GHz. The clock generator consumes 20.9mW from a 1.1V supply.

The paper presents a wideband, low-power chirp synthesizer for Ku-band FMCW radars. The DDS-driven ADPLL chirp synthesizer generates chirps up to 2GHz bandwidth. A low-power DDS is employed to generate a stepped reference frequency for ADPLL to ensure the long term chirp linearity, while the ADPLL fulfill the ramp-interpolating linearization by generating a narrow band chirp within the step frequency. The entire chirp benefits from the phase domain modulation and mitigates ADPLL loop bandwidth variation to achieve high linearity and low power. A novel adaptive ramping control scheme is adopted to ensure the chirp rate is constant after combining the narrow band chirp segments. By this two-stage chirp generation, a 2-GHz chirp is achieved with low relative frequency RMS error. Fabricated in a 65nm CMOS, the synthesizer generates a wideband chirp from 13.9GHz to 15.9GHz with configurable rate from 0.25 to 4GHz/ms, and consumes 53.8mW.

This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch mismatches on time skew is addressed. The measured time skew spurs caused by the sampling switch mismatches are around -52 to -55 dB at Nyquist input. Then, a tap-interpolating fractional delay filters-based digital background time skew calibration technique is proposed. Also, a full analysis of the effects of the various parameters on the time skew generated spur levels is presented, which indicates that the time skew error level is related to the length of calibration filters, calibration range, and bandwidth penalty. The subchannel ADC exploits a 250-MS/s SAR ADC with a low-cost high-speed subradix-2 searching technique. The reference interference of nonbinary TI ADCs is discussed and tolerated by the subradix-2 searching scheme. The proposed adders-based encoding circuit is optimized with lower propagation delay to meet high-speed requirements. The prototype was fabricated in a 65-nm CMOS technology. The measurement results show that the ADC achieves a signal-to-noise-plus-distortion ratio of 49.6 dB with a power of 15.95 mW and a figure of merit of 63 fJ/conversion step when operating at 1-GS/s and 458.1-MHz Nyquist input. The ADC core achieves an area of 0.158 mm2.

A Ku-band wideband power amplifier (PA) for FMCW radar application is proposed and implemented in 65-nm bulk CMOS technology. The PA consists of 3 stages of class AB amplifiers to achieve high gain and high power efficiency. To obtain low group delay (GD), low amplitude ripple and wide bandwidth, transformer and inductor based matching network is designed to meet the requirements. Including pads, the PA occupies a compact chip area of 0.62 mm2. Consuming 118 mA current from 1.2 V supply voltage, it demonstrates output saturation power of 13.04 dBm. The measured 3 dB bandwidth is 5.5 GHz with maximum gain 20.65 dB at 15.5 GHz. Finally, the PA is integrated with a (frequency modulated continuous wave) FMCW signal generator to constitute a FMCW radar transmitter.

A high gain decibel (dB)-linear programmable gain amplifier (PGA) for a synthetic aperture radar (SAR) receiver is presented in this paper. The proposed PGA employs binary-weighted switching array as pseudo-exponential function to achieve large dynamic range. A current compensation circuit is proposed in fine gain step cell to decrease gain step error. This PGA has been implemented in 65 nm CMOS technology embed ding in a SAR receiver. Measurement results show that the proposed PGA exhibits a dB-linear gain range of 60 dB from 10.47 to 69.63 dB with a gain error of less than ±0.39 dB, a input 1-dB compression point (IP-1dB) of -67.8 to -18.4 dBm, a 3-dB bandwidth of 0.8 to 50 MHz at the maximum gain while consuming less than 5.4 mA from a 1.2 V supply.

This live demonstration presents a first-in-kind fully integrated Ku-band Synthetic Aperture Radar (SAR) transceiver chip in 65-nm CMOS that fits for micro-UAVs. The transmitter presents 13.3-dBm output power and 1.48 GHz chirp bandwidth centering at 15 GHz. The receiver front-end attains 23.5-dB gain, -33-dBm IPldB and 5.6-to-6.3dB noise figure. The receiver analog baseband achieves 0.68-to-9.8-MHz programmable passband and 55-dB variable gain range. The integrated ADC has 9.4-bit ENOB. The SAR chip achieves super-resolution of 11.2 cm and consumes only 260-mW power. The ranging and imaging functions of the prototype are showcased.

This brief presents a low-computational, flexible nonbinary searching technique for high-speed successive approximation register (SAR) analog-to-digital converters (ADCs). By embedding the redundant weights into each capacitor branch of digital-to-analog converter (DAC) array, the conventional binary DAC array is customized as a nonbinary DAC array without additional control logics, resulting in fast conversion and negligible overhead. The weight of each branch could be defined flexibly with certain constraints, which is derived in this brief. Moreover, the nonbinary output codes are encoded to binary codes by adder-based encoding logics that show far less power and area penalty. To demonstrate the proposed nonbinary searching technique, a 10-bit 280-MS/s high-speed SAR-ADC is presented, which achieved an signal-to-noise-distortion ratio of 52.4 dB and a figure of merit of 21 fJ/conversion step.

In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, +0.005/fs].