A MOSFET model optimized for analog circuit simulation is presented and shown to agree with measured device characteristics, especially device output conductance and transconductance, over a wide range of operation. The widely used SPICE Level 3 (MOS3) model equations were utilized as a starting point in the model development process. The enhanced model (NMOD) exhibits smooth and continuous transitions in the weak to strong inversion region, and in the region between linear and saturation modes of device operation. These smooth transitions improve both the model's current and conductance prediction accuracy, as well as its convergence properties when used in circuit simulation. This is made possible because a single current equation is utilized for all regions of device operation. The NMOD model accurately characterizes devices over a wide range of geometries, achieving, for example, 1.3% and 4.2% average errors between measured and model I/sub DS/ and gds characteristics, respectively, for a 20/1.3- mu m p-channel device over a 5-V bias range.>

A method of modeling the distributed source and drain resistance effects in MOS transistors is discussed. Simulations performed using this technique are validated by comparisons with purpose-built structures. The method is then used to examine a problem which arises with the use of a high-temperature interconnect in three-dimensional silicon-on-insulator technologies. The results show how the resistivity of the interconnect affects the performance of the substrate devices of this technology, and the benefits achievable through further development of the existing interconnect technologies are outlined. Finally, the procedure is used to examine the effect of reduced contact size on standard MOS devices, and results wh1ich give general guidelines to the extent of the effect are presented.>