This paper proposes a novel Agile Physical Compiler (APCer) for multi-port register files based on a standard cell library. It employs a Performance, Power and Area (PPA)-driven genetic algorithm to facilitate agile iterations and design generation. APCer can automatically iterate, generate, and optimize floorplan, rapidly creating efficient register file circuits and layouts with specified capacity and port numbers. Additionally, APCer responds to user-defined PPA requirements, enabling targeted design optimizations. It accelerates the register file design duration by over 40× and 20× compared with the full custom approach and existing compilers, respectively. Compared to existing compilers, APCer improves performance by 20.7% and reduces power consumption by 33.9%. Compared to the full custom approach, APCer improves performance by 31.5% and reduces power consumption by 28.8%.

On-line control flow checking is able to detect wrong program execution paths caused by transient or intermittent hardware faults. Focusing on fault detection for YHFT-DSP, an embedded processor with very long instruction words (VLIW) structure, a hybrid control flow checking method (VLIW-CFC, V-CFC) based on signature monitoring is proposed. Signature instructions are designed for transmitting the redundancy information stored in signature and they are executed in unoccupied instruction slots to minimize the overhead of processor performance. Instruction signature is obtained by compressing instruction codes in a basic block, and it guarantees the execution integrality and correctness of this block. Branch signature is obtained from the program control flow graph (CFG) and dynamic offset signature instructions (DOSI), and it guarantees the correct execution sequences of multiple blocks. V-CFC with the two signatures is able to check control flow errors including execution sequences and bit flips of instruction codes. V-CFC reaches the high error-detection coverage, low performance loss and hardware costs, and it is well suited for embedded systems.