Efficient modular adder architectures are invaluable to the design of residue number system (RNS)-based digital systems. For example, they are used to perform residue encoding and decoding, modular multiplication, and scaling. This work is a first in the literature on modulo 2n-(2n-2+1) addition. The algebraic properties of such moduli are exploited in the derivation of the proposed fast adder architecture. Actual VLSI implementations using 130 mm CMOS technology show that our adder significantly outperforms the most competitive generic modular adder design over the entirety of the power-delay-area space

Novel modulo 2n-1 addition algorithms for residue number system (RNS) applications are presented. The proposed algorithms depart from the traditional approach of modulo 2n-1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures not only offer significant speedup in a modulo 2n-1 addition, but they can also offer a reduction in area and thus provide improvements in the cost functions area × delay2and energy × delay. The superiority of these architectures is validated through back-annotated VLSI designs using 130 nm CMOS technology.