This article presents a 13GS/s 9-bit 8-channel time-interleaved (TI) Pipelined-SAR (Pipe-SAR) ADC. A common-mode regulated floating-inverter-amplifier (CMR-FIA) is proposed to overcome the common-mode voltage variation due to the charge leakage through the parasitic capacitor, thereby eliminating the need for common-mode feedback (CMFB) circuitry embedded in the body of FIA. By combining an adaptively biased (AB) technique, the proposed FIA facilitates the high-speed and robust Pipe-SAR ADCs. In addition, a rapid-tracking bootstrapped signal generation is introduced to achieve high-linearity with short sampling time in an ultra-high speed sampling network. The ADC prototype is fabricated is a 28nm-CMOS process, the achieved spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) at the Nyquist input are 56.4dB and 41.75dB, respectively. Consuming 97mW at 13GS/s, it yields a Schreier figure of merit ($\text{FoM}_{\mathrm {S}}$) of 150dB. With the proposed CMR-FIA, the ADC’s SNDR variation is within 2.48dB across the input common-mode range of 0.3V to 0.8V.

Automated analog circuit design migration significantly alleviates the burden on designers in circuit sizing under various operating conditions. Conventional methods model the migration problem as black-box optimization, requiring excessive iterations of costly simulations to converge. Reinforcement learning exhibits significant promise in transfer learning, as it enables the generation of circuits that fulfill specifications efficiently. The paper proposes a novel value decomposition-based multi-agent reinforcement learning framework, aiming to model complex analog circuits and eliminate the need for manually defined specifications of sub-circuits for new operating conditions. Additionally, it incorporates domain randomization techniques to efficiently generate circuits that meet unforeseen scenarios with minimal simulations. Experiment demonstrates that our algorithm can efficiently generate circuits meeting specifications under new operating conditions in few number of steps, outperforming state-of-the-art methods.

Chiplet is a critical technology in the post-Moore era, and the die-to-die (D2D) interconnect is essential for communication between chiplets. Meanwhile, several edge-computing devices based on 2.5D/3D chiplet have recently emerged. However, a lightweight D2D interconnect for 2.5D/3D edge-computing systems is lacking. Given the differences between 2.5D/3D integration, a scalable D2D interconnect with replay and repair schemes is presented in this paper. A credit-based flow control scheme and a custom replay scheme are presented for high efficiency. An effective detection and repair scheme is proposed to enhance fault tolerance for the D2D interconnect. Compared with a previous D2D interconnect design, the proposed D2D interconnect delivers 1.07/1.09Gbps throughput ($\sim 2.4\times/\sim 3.9\times \text{for}\ \text{write}/\text{read}$) and significantly reduced energy/bit with only ∼1.7× increased hardware cost. Additionally, compared with a previous chip-to-chip interconnect design, the proposed D2D interconnect can be configured down to power consumption as low as 0.55pJ/bit and 38.40Gbps throughput, achieving ∼2.5× throughput and significantly reduced latency with a negligible increase in hardware cost.

This paper proposed a modified two-stage cascaded hybrid buck converter with reduced conduction loss, and simplified interleaving PWM circuit. The proposed converter reduces the conduction loss with fewer total switches and high-voltage switches. Also, the proposed converter achieves the inherent self-balanced flying capacitor voltages. Besides, the proposed converter simplifies the interleaving PWM circuit with the single ramp signal by digital logic. Moreover, the proposed converter avoids extra supply to feed the drivers. Simulated with a 130-nm BCD technology, the proposed converter regulates a 0.4 V - 1.2 V output from a 5 V input voltage, and it achieves the high peak and 1A-heavy-load efficiencies of 96% and 92.5%, respectively.

This paper proposes a modified interleaving resonant switched capacitor converter with reduced output resistance and in-situ startup. The operation principle, especially the average output voltage, the average flying capacitor voltages and the output resistance are theoretically deduced. The proposed converter reduces the output resistance by using less switches in some current paths. Besides, the proposed converter takes an in-situ flying capacitor pre-charge scheme to guarantee a safe startup. Here, we simulate both the conventional and the proposed converters in Cadence Spectre with the commercial device models. The proposed converter improves the heavy-load efficiency from 92.7% to 93.2% with$\mathrm{V}_{\text{IN}} = 48\ \mathrm{V}$and$\mathrm{V}_{\text{OUT}} = 12\ \mathrm{V}$, leading to around 7% total loss reduction.

This paper presents a single-channel two-stage pipelined-SAR ADC with ping-pong switched half of capacitor-digital-to-analog-converter (CDAC) moving the residue amplification into 2ndstage to lighten the timing burden of the 1ststage. Besides, a dynamic open-loop residue amplifier (RA) is employed to improve the energy efficiency and amplification speed. In order to enhance the ADC robustness, the gain variation under the supply and temperature drift are suppressed through the supply-and-temperature compensation bias. The simulation results shows gain variation is less than 5% under the temperature range from -20 °C to 100 °C and supply voltage variation of$\pm \mathbf{5}\%$, which ensure the above 56 dB ADC SNDR under process-voltage-temperature (PVT) variation. The ADC is simulated with a 40 nm CMOS process and 1V supply voltage, it achieves 59 dB SNDR with Nyquist input frequency at 1.25 GS/s sampling rate. The power consumption is 5.6mW, leading to a Walden FoM (FoMw) of 6.2 fJ/conversion-step and a Schreier FoM (FoMs) of 169.5 dB.

This paper presents a neural network-based digital calibration algorithm for high-speed and time-interleaved (TI) ADCs. In contrast with prior methods, the proposed work features joint amplitude-dependent and phase-dependent nonlinear distortion correction without prior-knowledge of ADC architecture feature. A dynamic calibration is first used to compensate for phase-dependent distortion. Two training optimizations, including a sub-range-sample-based batch schemes and a recursive foreground co-calibration flow are proposed to reduce the error and overfitting and further save hardware resources. A practical calibration engine is also investigated for interleaved ADCs with distributed weight and shared weight methods. To demonstrate the effectiveness of the method, the calibration engine is verified by two fabricated ADC prototypes, a 5 GS/s 16-way interleaved ADC and a 625 MS/s interleaving-SAR assisted pipeline ADC. Measurement results show that SFDR is improved between 16.9dB and 36.4dB before and after calibration for different frequency inputs. To trade-off between accuracy and power consumption, a quantized and pruned engine is implemented on both FPGA and 28nm CMOS technology. Experimental results show that the dedicated calibration on silicon consumes 8.64mW with 0.9V power supply at 333MHz clock rate. Measurement results show that the quantized hardware implementation has only 0.4-4 dB loss in SFDR.

This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3rdNyquist zone. The converter's front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers' inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC's power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step.