As chip design sizes continue to increase and they contain multiple instances of large and small cores, there is a need for a chip test architecture that allows efficient chip-level tests to be created while also reducing the memory and CPU time needed to create the tests. We define a hierarchical and core-based architecture for generating tests for cores and migrating them to the chip. This architecture allows testing multiple instances of the same core for the same cost as testing a single instance. The architecture also allows testing multiple instances of different cores as well. Memory use is kept low by generating tests for cores out of context and migrating them to the chip. We never have to build a full gate-level chip ATPG model. We show results of pattern count reduction possible when targeting multiple cores simultaneously.

At-speed testing with functional speed clocks is often done using On-Product Clock Generation (OPCG). When test compression logic is also embedded within the circuit's DFT architecture, the loading of the OPCG programming bits can impact test compression results. We present an approach to the use of OPCG that enables high-speed testing and is compatible with test compression. It also enables the use of tests that pulse multiple domains to further reduce test time and data volume. It also supports generation of inter-domain and static ATPG tests. We present results on four designs; one design shows an over 35% reduction in patterns due to use of multiple clock domains per test. An additional 10+% savings is possible using side-scan to load the OPCG programming registers.

On-product clock generation (OPCG) has been used for many years, often in conjunction with logic and memory BIST, but it is a labor-intensive process to identify the cut- points and the OPCG behavior so the ATPG tools can ignore the OPCG logic. Supporting programmable OPCG logic in an ASIC methodology flow required us to automate the OPCG test generation flow. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and show some results for a few real designs.

Although on-product clock generation (OPCG) has been used for many years, often in conjunction with Logic and Memory BIST, it has usually been a very manual process to identify the cut-points and the OPCG behavior to ATPG tools so they can avoid dealing directly with the OPCG logic. To support programmable OPCG logic in an ASIC methodology flow required us to find a way to automate the handling of the OPCG logic and the various clocking sequences it can produce. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and shows some results.

SmartBIST is a name for a family of streaming scan test pattern decoders that are suitable for on-chip integration. The automatic test pattern generation (ATPG) algorithms are modified to generate scan test stimulus vectors in a highly compacted source format that is compatible with the SmartBIST decoder hardware. The compacted stimulus vectors are streamed from automatic test equipment (ATE) to the decoder, which expands the data stream in real-time into fully expanded scan test vectors. SmartBIST encoding and decoding use simple algebraic techniques similar to those used for LFSR-coding (also known as LFSR-reseeding). The specific SmartBIST implementation shown in this paper guarantees that all test cubes can be successfully encoded by the modified ATPG algorithm irrespective of the number and position of the care bits.

This paper describes a simple test generation method for a high-performance, pipelined partial-scan microprocessor using an automatic test generation tool which was optimized for combinational logic in generating manufacturing test data. Without this method the test generation tool would have had great difficulty in generating the test data needed to achieve the required high fault coverage. User-specified clocking sequences are also allowed for design flexibility. A description of this method is provided and the experimental results are discussed.

This paper describes the test tool methodology used for the IBM S/390 microprocessor. An efficient, effective, and automated process providing correct-by-construction test pattern generation, an effective test pattern set, and diagnostics were required. This paper explains the techniques used to accomplish this along with explaining why the method was chosen and how it helped expedite the process.

This paper describes a weight generation algorithm that is driven by tests created by a test generator. New concepts with regard to throwing away ineffective weight sets are developed as an integral part of the system. Various parameters that help improve the effectiveness of the weight generation system are discussed.

This paper describes the design of an efficient weighted random pattern system. The performance of the system is measured by the number of weight sets and the number of weighted random patterns required for high fault coverage. Various heuristics that affect the performance of the system are discussed and an experimental evaluation is provided.