A low-power motion estimation chip is designed for a wireless panoramic endoscope system. This chip consists of two motion estimation cores and is implemented by a dual-Vdd low-power technique. The proposed technique is efficient in decreasing power consumption without reducing the operation frequency of the chip. From the full-function chip measurements, this dual-Vdd chip can reduce power consumption by 20%~40% than the operation in single-Vdd for different clock frequencies.

A low-power motion estimation chip is designed for a wireless panoramic endoscope system. This chip consists of two motion estimation cores and is implemented by a dual-Vdd low-power technique. The proposed technique is efficient in decreasing power consumption without reducing the operation frequency of the chip. From the full-function chip measurements, this dual-Vdd chip can reduce power consumption by 20%∼40% than the operation in single-Vdd at different clock frequencies.

In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.

Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.

Traditionally, it is assumed that every variable in the input HDL (hardware description language) behavioral description needs to be held in a register; a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been shown effective for signal-flow-like computations such as various DSP algorithms. However, the same is not true for the synthesis of control-dominated circuits, which usually have variables of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, some unclocked sequential networks or a combination of above. We identify the conditions in which the substitution is feasible. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register area minimization also generally leads to faster designs.

Traditionally, it is assumed that every variable in the input HDL (Hardware Description Language) behavioral description needs to be held in a register; A register can be shared by m ultiple variables if they have m utually disjoint lifetime intervals.This approach is eective for signal-ow-like computations such a s v arious DSP algorithms.However, it is not the best for the synthesis of control-dominated circuits, which usually have v ariables/signals of dierent bit-width as well as very long lifetime.To g o b ey ond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, or some unclocked sequential networks.We h a v e implemented the proposed method in a software program called VReg.Experimental results have demonstrated that VReg minimizes the number of registers more eectively than the lifetime-analysis-based approach does.Better register minimization also leads to both smaller area and faster designs.