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Nils Graef

dblp:57/7330 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Physical-layer communications · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Physical-layer communications › signal detection › maximum a posteriori detection
max-log-MAP detection		 0.112009
A low-complexity max-log-MAP detector · IEEE Trans. Commun. 2009
Physical-layer communications › signal detection
MIMO detection		 0.112009
A low-complexity max-log-MAP detector · IEEE Trans. Commun. 2009
Physical-layer communications › signal detection
soft-output detection		 0.112009
A low-complexity max-log-MAP detector · IEEE Trans. Commun. 2009
Integrated circuit design
digital circuit design		 0.012009
A low-complexity max-log-MAP detector · IEEE Trans. Commun. 2009
Integrated circuit design
low-power circuit design		 0.012009
A low-complexity max-log-MAP detector · IEEE Trans. Commun. 2009

Methods — techniques the papers use, named apart from their topics

parallelization · 0.2multiplier-free implementation · 0.2hierarchical metric computation · 0.2
YearPublicationVenuePosition
2009 A low-complexity max-log-MAP detector
abstract
A low-complexity soft-output Max-log-MAP (maximum a posteriori probability) detector for N2-QAM is exemplified for a 64-QAM 2timesM multiple-input-multiple-output (MIMO) system, exhibiting the following novel features: (1) hierarchical formulation of the exhaustive metric calculation to reduce the number of candidate tests by a factor of N per received symbol, and (2) multiplier-free implementation of the exhaustive search with 8-fold parallelization. The computational complexity is reduced by a factor of about 250, resulting in a chip area of 0.031 mm2using 65 nm CMOS.
Nils Graef, Joachim S. Hammerschmidt, Carl-Erik W. Sundberg
 IEEE Trans. Commun.1