VLDB 2026 Research / reviewers in the wild / expert
Abhishek Dhanotia
dblp:58/10369
· DBLP profile ↗
11ranked-venue papers
0as first author
8since 2021 · last 2026
0000-0002-5916-9383ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 10 · 8 since 2021Systems, architecture and hardware · 8 · 6 since 2021Computer networks · 1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Power Sloshing in Compound Servers for Large-Scale AI Inference Workloads
Albert Cho, Jovan Stojkovic, Leonardo Piga, Abhishek Dhanotia, Sultan Mahmud Sajal, Gefei Zuo, Krishna T. Malladi, Devon Akers, Kalyan Subramanian, Shobhit O. Kanaujia, Alexandros Daglis |
ISCA | 4 |
| 2026 | Vistara: Making CXL Real-Full Path From ASIC Design and OS Support to Hyperscale Deployment
Neha Gholkar, Jovan Stojkovic, Hasan Al Maruf, Gregory Price, Prakash Chauhan, Hiral Patel, Cedric Van Goethem Kiran Vemuri, Kiran Malwankar, Kishore Sriadibhatla, Kalyan Subramanian, Shobhit O. Kanaujia, Chunqiang Tang, Abhishek Dhanotia |
ISCA | 13 |
| 2025 | DCPerf: An Open-Source, Battle-Tested Performance Benchmark Suite for Datacenter WorkloadsabstractWe present DCPerf, the first open-source performance benchmark suite actively used to inform procurement decisions for millions of CPU in hyperscale datacenters.Although numerous benchmarks exist, our evaluation reveals that they inaccurately project server performance for datacenter workloads or fail to scale to resemble production workloads on modern many-core servers.DCPerf distinguishes itself in two aspects: (1) it faithfully models essential software architectures and features of datacenter applications, such as microservice architecture and highly optimized multi-process or multi-thread concurrency; and (2) it strives to align its performance characteristics with those of production workloads, at both the system level and microarchitecture level.Both are made possible by our direct access to the source code and hyperscale production deployments of datacenter workloads.Additionally, we share real-world examples of using DCPerf in critical decision-making, such as selecting future CPU SKUs and guiding CPU vendors in optimizing their designs.Our evaluation demonstrates that DCPerf accurately projects the performance of representative production workloads within a 3.3% error margin across four generations of production servers introduced over a span of six years, with core counts varying widely from 36 to 176. Wei Su 0005, Abhishek Dhanotia, Jayneel Gandhi, Neha Gholkar, Shobhit O. Kanaujia, Maxim Naumov, Kalyan Subramanian, Valentin Andrei, Chunqiang Tang |
ISCA | 2 |
| 2024 | Expanding Datacenter Capacity with DVFS Boosting: A safe and scalable deployment experienceabstractCOVID-19 pandemic created unexpected demand for our physical infrastructure. We increased our computing supply by growing our infrastructure footprint as well as expanded existing capacity by using various techniques among those DVFS boosting. This paper describes our experience in deploying DVFS boosting to expand capacity. Leonardo Piga, Iyswarya Narayanan, Aditya Sundarrajan, Matt Skach, Qingyuan Deng, Biswadip Maity, Manoj Chakkaravarthy, Alison Huang, Abhishek Dhanotia, Parth Malani |
ASPLOS (1) | 9 |
| 2023 | Ditto: End-to-End Application Cloning for Networked Cloud ServicesabstractThe lack of representative, publicly-available cloud services has been a recurring problem in the architecture and systems communities. While open-source benchmarks exist, they do not capture the full complexity of cloud services. Application cloning is a promising way to address this, however, prior work is limited to CPU-/cache-centric, single-node services, operating at user level. Mingyu Liang, Yu Gan 0002, Abhishek Dhanotia, Mahesh Ketkar, Christina Delimitrou |
ASPLOS (2) | 5 |
| 2023 | TPP: Transparent Page Placement for CXL-Enabled Tiered-MemoryabstractThe increasing demand for memory in hyperscale applications has led to memory becoming a large portion of the overall datacenter spend. The emergence of coherent interfaces like CXL enables main memory expansion and offers an efficient solution to this problem. In such systems, the main memory can constitute different memory technologies with varied characteristics. In this paper, we characterize memory usage patterns of a wide range of datacenter applications across the server fleet of Meta. We, therefore, demonstrate the opportunities to offload colder pages to slower memory tiers for these applications. Without efficient memory management, however, such systems can significantly degrade performance. Hasan Al Maruf, Hao Wang 0011, Abhishek Dhanotia, Johannes Weiner, Niket Agarwal, Pallab Bhattacharya, Chris Petersen 0002, Mosharaf Chowdhury, Shobhit O. Kanaujia, Prakash Chauhan |
ASPLOS (3) | 3 |
| 2023 | Characterization of Data Compression in DatacentersabstractData compression has emerged as a promising technique to alleviate the memory, storage, and network cost with some associated compute overheads in warehouse-scale datacenter services. Despite being one of the most important components of the overall datacenter taxes, there has not been a comprehensive characterization of compression usage in datacenter workloads. Such characterization is paramount for both compression software developers and hardware accelerator designers as it can help them make optimal design trade-offs decisions in terms of performance, power, and cost while meeting service-level agreements of target applications. Moreover, it can provide data-driven insights to application developers to find optimal compression configuration choices for their services. In this paper, we first provide a holistic characterization of compression as used by various warehouse-scale datacenter services at a global social media provider, Meta. Next, we deep dive into a few representative use cases of compression in the production environment and characterize compression usage of the services while running live traffic. Finally, we conduct sensitivity studies to understand how different compression configurations are relevant to the overall infrastructure cost, followed by future research directions for compression hardware and software development. Geonhwa Jeong, Bikash Sharma, Nick Terrell, Abhishek Dhanotia, Niket Agarwal, Arun Kejariwal, Tushar Krishna |
ISPASS | 4 |
| 2022 | Understanding Data Compression in Warehouse-Scale Datacenter ServicesabstractData compression has emerged as a promising technique to alleviate the memory, storage, and network cost with some associated compute overheads in warehouse-scale datacenter services. Despite being one of the most important components of the overall datacenter taxes, there has not been a comprehensive characterization of compression usage in data center workloads. In this work, we first provide a holistic characterization of compression as used by various warehouse-scale datacenter services at a global social media provider (Meta). Next, we deep dive into a few representative use cases of compression in the production environment and characterize compression usage of services while running live traffic. Geonhwa Jeong, Bikash Sharma, Nick Terrell, Abhishek Dhanotia, Niket Agarwal, Arun Kejariwal, Tushar Krishna |
ISPASS | 4 |
| 2020 | Accelerometer: Understanding Acceleration Opportunities for Data Center Overheads at HyperscaleabstractAt global user population scale, important microservices in warehouse-scale data centers can grow to account for an enormous installed base of servers. With the end of Dennard scaling, successive server generations running these microservices exhibit diminishing performance returns. Hence, it is imperative to understand how important microservices spend their CPU cycles to determine acceleration opportunities across the global server fleet. To this end, we first undertake a comprehensive characterization of the top seven microservices that run on the compute-optimized data center fleet at Facebook. Akshitha Sriraman, Abhishek Dhanotia |
ASPLOS | 2 |
| 2019 | SoftSKU: optimizing server architectures for microservice diversity @scaleabstractThe variety and complexity of microservices in warehouse-scale data centers has grown precipitously over the last few years to support a growing user base and an evolving product portfolio. Despite accelerating microservice diversity, there is a strong requirement to limit diversity in underlying server hardware to maintain hardware resource fungibility, preserve procurement economies of scale, and curb qualification/test overheads. As such, there is an urgent need for strategies that enable limited server CPU architectures (a.k.a "SKUs") to provide performance and energy efficiency over diverse microservices. To this end, we first undertake a comprehensive characterization of the top seven microservices that run on the compute-optimized data center fleet at Facebook. Akshitha Sriraman, Abhishek Dhanotia, Thomas F. Wenisch |
ISCA | 2 |
| 2011 | A Canonical Multicore Architecture for Network RoutersabstractThere has been a significant increase in the Internet dynamics in the past decade. This has put tremendous pressure on the performance of routing protocols as they need to keep updating their routing information with every network change across the globe. With the growth of Internet, Border Gateway Protocol (BGP) has become a critical routing application. Good performance of BGP on network processors directly translates to better convergence time for route changes on the Internet, leading to reduced data loss on the network. BGP is the ubiquitous routing protocol on the Internet core, and hence analyzing its performance and exploring avenues for speeding it up can greatly help in improving the responsiveness and reliability of the Internet. In this paper, we investigate the use of multicore as the compute platform for routing protocols using BGP as a representative application. We discuss two different schemes for parallelizing BGP and analyze the performance of both serial and parallel BGP implementations on a fully configurable multicore simulation environment. Subsequently, we analyze the architectural bottlenecks in the conventional multicore systems which limit the speedup that can be achieved by software parallelism alone, and propose a canonical multicore architecture for routing protocols, which can be used for future routing processor designs. The analysis and proposed schemes in this paper would greatly help in understanding the behavior of BGP, thereby assisting in design and development of next generation network processors. Sabina Grover, Abhishek Dhanotia, Greg Byrd |
ANCS | 2 |