In this paper, we present a heuristic algorithm that improves the performance of static task scheduling. Our algorithm is based on the list-scheduling mechanism. For the listing phase, we use existing techniques to generate partial-order task sequences based on critical-path-first ordering, critical-task-first ordering, and their hybrids. For the scheduling phase, we propose a task-duplication algorithm with a look-ahead technique, so that the complexity of the new algorithm does not increase. The experiment results show that our algorithm outperforms other algorithms for any feasible task sequences with respect to the average execution times and the average scheduling length ratios.

Partitioning meshes is a preprocessing step for parallel scientific simulation. The quality of a partitioning is measured by load balance and communication overhead. The effectiveness of a partitioning significantly influences the performance of parallel computation. In this paper, we propose a quadtree spatial-based domain decomposition method for partitioning unstructured meshes. The background quadtree, which is originally used to represent the density distribution among elements within the computing domain, can be used to obtain an initial partitioning and to do multi-level refinement. As the quadtree implicitly defines hierarchical relationship, which is a natural way to define coarsening and uncoarsening phases, we can repeatedly apply coarsening, partitioning, and uncoarsening multilevel refinement phases, until no improvement can be made. Thus, for most cases, the partitioning results by our method are better than those produced by other graph-based partitioning methods. Experimental studies for the NACA0012 airfoil, the NASA EET wing, and an artillery shell within a shock tube are reported.

To exploit parallelism on shared memory parallel computers (SMPCs), it is natural to focus on decomposing the computation (mainly by distributing the iterations of the nested Do-Loops). In contrast, on distributed memory parallel computers (DMPCs), the decomposition of computation and the distribution of data must both be handled---in order to balance the computation load and to minimize the migration of data. We propose and validate experimentally a method for handling computations and data synergistically to minimize the overall execution time on DMPCs. The method is based on a number of novel techniques, also presented in this article. The core idea is to rank the "importance" of data arrays in a program and specify some of the dominant. The intuition is that the dominant arrays are the ones whose migration would be the most expensive. Using the correspondence between iteration space mapping vectors and distributed dimensions of the dominant data array in each nested Do-loop, allows us to design algorithms for determining data and computation decompositions at the same time. Based on data distribution, computation decomposition for each nested Do-loop is determined based on either the "owner computes" rule or the "owner stores" rule with respect to the dominant data array. If all temporal dependence relations across iteration partitions are regular, we use tiling to allow pipelining and the overlapping of computation and communication. However, in order to use tiling on DMPCs, we needed to extend the existing techniques for determining tiling vectors and tile sizes, as they were originally suited for SMPCs only. The overall method is illustrated on programs for the 2D heat equation, for the Gaussian elimination with pivoting, and for the 2D fast Fourier transform on a linear processor array and on a 2D processor grid.

Data distribution has been one of the most important research topics in parallelizing compilers for distributed memory parallel computers. Good data distribution schema should consider both the computation load balance and the communication overhead. In this paper, we show that data redistribution is necessary for executing a sequence of Do-loops if the communication cost due to performing this sequence of Do-loops is larger than a threshold value. Based on this observation, we can prune the searching space and derive efficient dynamic programming algorithms for determining effective data distribution schema to execute a sequence of Do-loops with a general structure. Experimental studies on a 32-node nCUBE-2 computer are also presented.

In this paper, we present a systhetic method for compiling programs on distributed memory parallel computers.

Consideration is given to transforming depth p-nested for loop algorithms into q-dimensional systolic VLSI arrays where 1>

A simple programmable linear systolic array capable of solving a large number of problems drawn from a variety of applications is designed. The methodology is applicable to problems solvable by sequential algorithms that can be specified as nested FOT-loops of arbitrary depth. The algorithms of this form that can be computed on the array include 25 algorithms dealing with signal and image processing, algebraic computations, matrix arithmetic, pattern matching, database operations, sorting, and transitive closure. Assuming bounded I/O, for 18 of those algorithms the time and storage complexities are optimal, and therefore no improvement can be expected by utilizing dedicated special-purpose linear systolic arrays designed for individual algorithms.>

The mapping of algorithms structured as depth-p nested FOR loops into special-purpose systolic VLSI linear arrays is addressed. The mappings are done by using linear functions to transform the original sequential algorithms into a form suitable for parallel execution on linear arrays. A feasible mapping is derived by identifying formal criteria to be satisfied by both the original sequential algorithm and the proposed transformation function. The methodology is illustrated by synthesizing algorithms for matrix multiplication and a version of the Warshall-Floyd transitive closure algorithm.>