Machine learning-assisted global optimization methods for speeding up analog integrated circuit sizing is attracting much attention. However, often a few typical analog integrated circuit design specifications are considered in most relevant research. When considering the complete set of specifications, two main challenges are yet to be addressed: 1) the prediction error for some performances may be large and the prediction error is accumulated by many performances. This may mislead the optimization and fail the sizing, especially when the specifications are stringent and 2) the machine learning cost could be high considering the number of specifications, considerably canceling out the time saved. A new method, called efficient surrogate model-assisted sizing method for high-performance analog building blocks (ESSAB), is proposed in this article to address the above challenges. The key innovations include a new candidate design ranking method and a new artificial neural network model construction method for analog circuit performance. Experiments using two amplifiers and a comparator with a complete set of stringent design specifications show the advantages of ESSAB.

Analog circuit sizing takes a significant amount of manual effort in a typical design cycle. With rapidly developing technology and tight schedules, bringing automated solutions for sizing has attracted great attention. This paper presents DNN-Opt, a Reinforcement Learning (RL) inspired Deep Neural Network (DNN) based black-box optimization framework for analog circuit sizing. The key contributions of this paper are a novel sample-efficient two-stage deep learning optimization framework leveraging RL actor-critic algorithms, and a recipe to extend it on large industrial circuits using critical device identification. Our method shows 5—30x sample efficiency compared to other black-box optimization methods both on small building blocks and on large industrial circuits with better performance metrics. To the best of our knowledge, this is the first application of DNN-based circuit sizing on industrial scale circuits.

A challenge in engineering design optimization is that sufficient information may not be available to define the exact specifications beforehand. While iterative trial optimization using different specifications is widely used in industry, multiobjective optimization is attracting much attention in the academic field. However, off-the-shelf methods in both categories are time-consuming due to the involved computationally expensive simulations. In this paper, the characteristics of the targeted problem are summarized; the gap between off-the-shelf methods and the practical need is then analyzed. A simple yet effective framework, called two-stage multi-fidelity surrogate model-assisted optimization (TMSO), is proposed to improve efficiency. TSMO is implemented by two state-of-the-art optimization algorithms and two real-world design cases demonstrate its effectiveness in practice. The research topics in multiobjective optimization and surrogate model-assisted optimization inspired by the TSMO framework is finally discussed.

Real-world computationally expensive design optimization problems with discrete variables pose challenges to surrogate-based optimization methods in terms of both efficiency and search ability. In this paper, a new method is introduced, called surrogate model-aware differential evolution with neighbourhood exploration, which has two phases. The first phase adopts a surrogate-based optimization method based on efficient surrogate model-aware search framework, the goal of which is to reach at least the neighbourhood of the global optimum. In the second phase, a neighbourhood exploration method for discrete variables is developed and collaborates with the first phase to further improve the obtained solutions. Empirical studies on various benchmark problems and a real-world network-on-chip design optimization problem show the combined advantages in terms of efficiency and search ability: when only a very limited number of exact evaluations are allowed, the proposed method is not slower than one of the most efficient methods for the targeted problem; when more evaluations are allowed, the proposed method can obtain results with comparable quality compared to standard differential evolution, but it requires only 1% to 30% of exact function evaluations.

Stable matching-based selection models the selection process in MOEA/D as a stable marriage problem. By finding a stable matching between the sub problems and solutions, the solutions are assigned to sub problems to balance the convergence and the diversity. In this paper, a two-level stable matching-based selection is proposed to further guarantee the diversity of the population. More specifically, the first level of stable matching only matches a solution to one of its most preferred sub problems and the second level of stable matching is responsible for matching the solutions to the remaining sub problems. Experimental studies demonstrate that the proposed selection scheme is effective and competitive comparing to other state-of-the-art selection schemes for MOEA/D.

The surrogate model-aware evolutionary search (SMAS) framework is an emerging model management method for surrogate model assisted evolutionary algorithms (SAEAs). SAEAs based on SMAS outperform several state-of-the-art SAEAs using other model management methods and show promising results in real-world computationally expensive optimization problems. However, there is little behavioral study of the SMAS framework, and appropriate rules for its search strategy, training data selection and key parameter selection for different types of problems have not been provided yet. In this paper, with a newly proposed training data selection method, the SMAS framework's behaviour with different search strategies and training data selection methods is investigated. The empirical rules in terms of problem characteristics are obtained and the method to construct an SAEA based on the SMAS framework is updated. Experiments using 24 widely used benchmark test problems and the test problems in the CEC 2014 competition of computationally expensive optimization are carried out, which validate the proposed empirical rules.

Network-on-Chip (NoC) design is attracting more and more attention nowadays, but there is a lack of design optimization method due to the computationally very expensive simulations of NoC. To address this problem, an algorithm, called NoC design optimization based on Gaussian process model assisted differential evolution (NDPAD), is presented. Using the surrogate model-aware evolutionary search (SMAS) framework with the tournament selection based constraint handling method, NDPAD can obtain satisfactory solutions using a limited number of expensive simulations. The evolutionary search strategies and training data selection methods are then investigated to handle integer design parameters in NoC design optimization problems. Comparison shows that comparable or even better design solutions can be obtained compared to standard EAs, and much less computation effort is needed.

The design and optimization (both sizing and layout) of mm-wave integrated circuits (ICs) have attracted much attention due to the growing demand in industry. However, available manual design and synthesis methods suffer from a high dependence on design experience, being inefficient or not general enough. To address this problem, a new method, called general mm-wave IC synthesis based on Gaussian process model assisted differential evolution (GASPAD), is proposed in this paper. A medium-scale computationally expensive constrained optimization problem must be solved for the targeted mm-wave IC design problem. Besides the basic techniques of using a global optimization algorithm to obtain highly optimized design solutions and using surrogate models to obtain a high efficiency, a surrogate model-aware search mechanism (SMAS) for tackling the several tens of design variables (medium scale) and a method to appropriately integrate constraint handling techniques into SMAS for tackling the multiple (high-) performance specifications are proposed. Experiments on two 60 GHz power amplifiers in a 65 nm CMOS technology and two mathematical benchmark problems are carried out. Comparisons with the state-of-art provide evidence of the important advantages of GASPAD in terms of solution quality and efficiency.

Surrogate model assisted evolutionary algorithms (SAEAs) have recently attracted much attention due to the growing need for computationally expensive optimization in many real-world applications. Most current SAEAs, however, focus on small-scale problems. SAEAs for medium-scale problems (i.e., 20-50 decision variables) have not yet been well studied. In this paper, a Gaussian process surrogate model assisted evolutionary algorithm for medium-scale computationally expensive optimization problems (GPEME) is proposed and investigated. Its major components are a surrogate model-aware search mechanism for expensive optimization problems when a high-quality surrogate model is difficult to build and dimension reduction techniques for tackling the “curse of dimensionality.” A new framework is developed and used in GPEME, which carefully coordinates the surrogate modeling and the evolutionary search, so that the search can focus on a small promising area and is supported by the constructed surrogate model. Sammon mapping is introduced to transform the decision variables from tens of dimensions to a few dimensions, in order to take advantage of Gaussian process surrogate modeling in a low-dimensional space. Empirical studies on benchmark problems with 20, 30, and 50 variables and a real-world power amplifier design automation problem with 17 variables show the high efficiency and effectiveness of GPEME. Compared to three state-of-the-art SAEAs, better or similar solutions can be obtained with 12% to 50% exact function evaluations.

In engineering design and manufacturing optimization, the trade-off between a quality performance metric and the probability of satisfying all performance specifications (yield) of a product naturally leads to a chance-constrained bi-objective stochastic optimization problem (CBSOP). A new method, called MOOLP (multi-objective uncertain optimization with ordinal optimization (OO)), Latin supercube sampling and parallel computation), is proposed in this paper for dealing with the CBSOP. This proposed method consists of a constraint satisfaction phase and an objective optimization phase. In its constraint satisfaction phase, by using the OO technique, an adequate number of samples are allocated to promising solutions, and the number of unnecessary MC simulations for noncritical solutions can be reduced. This can achieve more than five times speed enhancement compared to the application of using an equal number of samples for each candidate solution. In its MOEA/D-based objective optimization phase, by using LSS, more than five times speed enhancement can be achieved with the same estimation accuracy compared to primitive MC simulation. Parallel computation is also used for speedup. A real-world problem of the bi-objective variation-aware sizing for an analog integrated circuit is used in this paper as a practical application. The experiments clearly demonstrate the advantages of MOOLP.

Surrogate model assisted evolutionary algorithms are receiving much attention for the solution of optimization problems with computationally expensive function evaluations. For small scale problems, the use of a Gaussian Process surrogate model and prescreening methods has proven to be effective. However, each commonly used prescreening method is only suitable for some types of problems, and the proper prescreening method for an unknown problem cannot be stated beforehand. In this paper, the four existing prescreening methods are analyzed and a new method, called self-adaptive lower confidence bound (ALCB), is proposed. The extent of rewarding the prediction uncertainty is adjusted on line based on the density of samples in a local area and the function properties. The exploration and exploitation ability of prescreening can thus be better balanced. Experimental results on benchmark problems show that ALCB has two main advantages: (1) it is more general for different problem landscapes than any of the four existing prescreening methods; (2) it typically can achieve the best result among all available prescreening methods.

Multi-objective synthesis for microwave components (e.g. integrated transformer, antenna) is in high demand. Since the embedded electromagnetic (EM) simulations make these tasks very computationally expensive when using traditional multi-objective synthesis methods, efficiency improvement is very important. However, this research is almost blank. In this paper, a new method, called Gaussian Process assisted multi-objective optimization with generation control (GPMOOG), is proposed. GPMOOG uses MOEA/D-DE as the multi-objective optimizer, and a Gaussian Process surrogate model is constructed ON-LINE to predict the results of expensive EM simulations. To avoid false optima for the on-line surrogate model assisted evolutionary computation, a generation control method is used. GPMOOG is demonstrated by a 60GHz integrated transformer, a 1.6GHz antenna and mathematical benchmark problems. Experiments show that compared to directly using a multi-objective evolutionary algorithm in combination with an EM simulator, which is the best known method in terms of solution quality, comparable results can be obtained by GPMOOG, but at about 1/3-1/4 of the computational effort.

Yield estimation for analog integrated circuits remains a time-consuming operation in variation-aware sizing. State-of-the-art statistical methods such as ranking-integrated Quasi-Monte-Carlo (QMC), suffer from performance degradation if the number of effective variables is large (as typically is the case for realistic analog circuits). To address this problem, a new method, called AYLeSS, is proposed to estimate the yield of analog circuits by introducing Latin Supercube Sampling (LSS) technique from the computational statistics field. Firstly, a partitioning method is proposed for analog circuits, whose purpose is to appropriately partition the process variation variables into low-dimensional sub-groups fitting for LSS sampling. Then, randomized QMC is used in each sub-group. In addition, the way to randomize the run order of samples in Latin Hypercube Sampling (LHS) is used for the QMC sub-groups. AYLeSS is tested on 4 designs of 2 example circuits in 0.35μm and 90nm technologies with yield from about 50% to 90%. Experimental results show that AYLeSS has approximately a 2 times speed enhancement compared with the best state-of-the-art method.

Existing radio frequency (RF) integrated circuit (IC) design automation methods focus on the synthesis of circuits at a few GHz, typically less than 10 GHz. That framework is difficult to apply to RF IC synthesis at mm-wave frequencies (e.g., 60-100 GHz). In this paper, a new method, called efficient machine learning-based differential evolution, is presented for mm-wave frequency linear RF amplifier synthesis. By using electromagnetic (EM) simulations to evaluate the key passive components, the evaluation of circuit performances is accurate and solves the limitations of parasitic-included equivalent circuit models and predefined layout templates used in the existing synthesis framework. A decomposition method separates the design variables that require expensive EM simulations and the variables that only need cheap circuit simulations. Hence, a low- dimensional expensive optimization problem is generated. By the newly proposed core algorithm integrating adaptive population generation, naive Bayes classification, Gaussian process and differential evolution, the generated low-dimensional expensive optimization problem can be solved efficiently (by the online surrogate model), and global search (by evolutionary computation) can be achieved. A 100 GHz three-stage differential amplifier is synthesized in a 90 nm CMOS technology. The power gain reaches 10 dB with more than 20 GHz bandwidth. The synthesis costs only 25 h, having a comparable result and a nine times speed enhancement compared with directly using the EM simulator and global optimization algorithms.

Design and optimization of microwave passive components is one of the most critical problems for RF IC designers. However, the state-of-the-art methods either have good efficiency but highly depend on the accuracy of the equivalent circuit models, which may fail the synthesis when the frequency is high; or fully depend on electromagnetic (EM) simulations, whose solution quality is high but are too expensive. To address the problem, a new method, called Gaussian Process-Based Differential Evolution for Constrained Optimization (GPDECO) is proposed. In particular, GPDECO performs global optimization of the microwave structure using EM simulations, and a Gaussian process (GP) based surrogate model is constructed ON-LINE at the same time to predict the results of expensive EM simulations. GPDECO is tested by two 60GHz transformers and comparisons with the state-of-the-art methods are performed. The results show that GPDECO can generate high performance RF passive components that cannot be generated by the available efficient methods. Compared with available methods with the best solution quality, GPDECO can achieve comparable results but only costs 20%-25% of the computational effort. Using parallel computation in an 8-core CPU, the synthesis can be finished in less than 0.5 hour.

It is known that the operating-point driven (OPD) analog sizing methods have clear advantages compared with the sizing methods of directly using transistor width and length as the decision variables. However, new analog sizing algorithms using OPD technique in modern technologies have seldom been reported in recent years. One of the main reasons is that with the scaling down of the technologies, the transistor models are much more complex, which makes the available DC root solving algorithms and the look-up-table-based methods face significant challenges on accuracy, efficiency and memory requirements. Instead of solving the equations to find the width of transistors, interpolating in a pre-constructed look-up-table, or using regression methods, a novel method, called on-line interpolation operating-point driven (OIOPD), is proposed. OIOPD finds the width of the transistor by the interpolation of the width-current curve with already determined length and voltage biases. The lower and upper points to decide the interpolated value are generated by on-line simulations using the two extreme values of the width in a technology. Experimental results in 0.25μm, 0.18 μm and 90nm technologies show that OIOPD has 10 times improvement on accuracy, 300-1100 times improvement on efficiency compared with the available methods. In addition, no extra memory (e.g. the memory to save the look-up table) is needed. These advantages make OIOPD suitable for operating-point driven analog sizing methods in modern technologies. A practical analog sizing example using OIOPD is also provided.

In nanometer complementary metal-oxide-semiconductor technologies, worst-case design methods and response-surface-based yield optimization methods face challenges in accuracy. Monte-Carlo (MC) simulation is general and accurate for yield estimation, but its efficiency is not high enough to make MC-based analog yield optimization, which requires many yield estimations, practical. In this paper, techniques inspired by computational intelligence are used to speed up yield optimization without sacrificing accuracy. A new sampling-based yield optimization approach, which determines the device sizes to optimize yield, is presented, called the ordinal optimization (OO)-based random-scale differential evolution (ORDE) algorithm. By proposing a two-stage estimation flow and introducing the OO technique in the first stage, sufficient samples are allocated to promising solutions, and repeated MC simulations of non-critical solutions are avoided. By the proposed evolutionary algorithm that uses differential evolution for global search and a random-scale mutation operator for fine tunings, the convergence speed of the yield optimization can be enhanced significantly. With the same accuracy, the resulting ORDE algorithm can achieve approximately a tenfold improvement in computational effort compared to an improved MC-based yield optimization algorithm integrating the infeasible sampling and Latin-hypercube sampling techniques. Furthermore, ORDE is extended from plain yield optimization to process-variation-aware single-objective circuit sizing.

State-of-the-art synthesis methods for microwave passive components suffer from the following drawbacks. They either have good efficiency but highly depend on the accuracy of the equivalent circuit models, which may fail the synthesis when the frequency is high, or they fully depend on electromagnetic (EM) simulations, with a high solution quality but are too time consuming. To address the problem of combining high solution quality and good efficiency, a new method, called memetic machine learning-based differential evolution (MMLDE), is presented. The key idea of MMLDE is the proposed online surrogate model-based memetic evolutionary optimization mechanism, whose training data are generated adaptively in the optimization process. In particular, by using the differential evolution algorithm as the optimization kernel and EM simulation as the performance evaluation method, high-quality solutions can be obtained. By using Gaussian process and artificial neural network in the proposed search mechanism, surrogate models are constructed online to predict the performances, saving a lot of expensive EM simulations. Compared with available methods with the best solution quality, MMLDE can obtain comparable results, and has approximately a tenfold improvement in computational efficiency, which makes the computational time for optimized component synthesis acceptable. Moreover, unlike many available methods, MMLDE does not need any equivalent circuit models or any coarse-mesh EM models. Experiments of 60 GHz syntheses and comparisons with the state-of-art methods provide evidence of the important advantages of MMLDE.

Recently, a multiobjective evolutionary algorithm based on decomposition (MOEA/D) and its extended version by using differential evolution (DE) as the main search engine (MOEA/D-DE) were proposed, which outperform several widely used multiobjective evolutionary algorithms. MOEA/D decomposes a multiobjective problem into a number of scalar optimization sub-problems with a neighborhood structure and optimizes them simultaneously to approximate the Pareto-optimal set. In this paper, two mechanisms are investigated to enhance the performance of MOEA/D-DE. Firstly, a new replacement mechanism is proposed to call for a balance between the diversity of the population and the employment of good information from neighbors. Secondly, the scaling factor in DE is randomized to enhance the search ability. Comparisons are carried out with MOEA/D-DE on ten benchmark problems, showing that the proposed method exhibits significant improvements. Finally, the enhanced MOEA/D-DE is applied to a real world problem, the sizing of a folded-cascode amplifier with four performance objectives.

Monte-Carlo (MC) simulation is still the most commonly used technique for yield estimation of analog integrated circuits, because of its generality and accuracy. However, although some speed acceleration methods for MC simulation have been proposed, their efficiency is not high enough for MC-based yield optimization (determines optimal device sizes and optimizes yield at the same time), which requires repeated yield calculations. In this paper, a new sampling-based yield optimization approach is presented, called the Memetic Ordinal Optimization (OO)-based Hybrid Evolutionary Constrained Optimization (MOHECO) algorithm, which significantly enhances the efficiency for yield optimization while maintaining the high accuracy and generality of MC simulation. By proposing a two-stage estimation flow and introducing the OO technology in the first stage, sufficient samples are allocated to promising solutions, and repeated MC simulations of non-critical solutions are avoided. By the proposed memetic search operators, the convergence speed of the algorithm can considerably be enhanced. With the same accuracy, the resulting MOHECO algorithm can achieve yield optimization by approximately 7 times less computational effort compared to a state-of-the-art MC-based algorithm integrating the acceptance sampling (AS) plus the Latin-hypercube sampling (LHS) techniques. Experiments and comparisons in 0.35 ¿m and 90 nm CMOS technologies show that MOHECO presents important advantages in terms of accuracy and efficiency.

In this paper, a fuzzy selection-based differential evolution algorithm (FSBDE) for analog cell sizing is investigated. By combining the selection-based constraint handling method and fuzzy membership functions, a new selection methodology for handling fuzzy constraints is proposed and is integrated with the differential evolution (DE) algorithm to construct FSBDE. FSBDE specializes in solving analog sizing problems capturing imprecise human intentions, both avoiding the inflexibility of crisp constraint sizing methods and the excessive relaxation of available fuzzy sizing approaches. The high optimization ability of the DE algorithm is also inherited in this approach. Comparisons are carried out with the crisp selection-based differential evolution algorithm (SBDE) and DE in conjunction with available fuzzy optimization methods, showing that the proposed FSBDE algorithm presents important advantages in terms of fuzzy constraint handling ability and optimization quality.

This article introduces an evolution-based methodology, named memetic single-objective evolutionary algorithm (MSOEA), for automated sizing of high-performance analog integrated circuits. Memetic algorithms may achieve higher global and local search ability by properly combining operators from different standard evolutionary algorithms. By integrating operators from the differential evolution algorithm, from the real-coded genetic algorithm, operators inspired by the simulated annealing algorithm, and a set of constraint handling techniques, MSOEA specializes in handling analog circuit design problems with numerous and tight design constraints. The method has been tested through the sizing of several analog circuits. The results show that design specifications are met and objective functions are highly optimized. Comparisons with available methods like genetic algorithm and differential evolution in conjunction with static penalty functions, as well as with intelligent selection-based differential evolution, are also carried out, showing that the proposed algorithm has important advantages in terms of constraint handling ability and optimization quality.

A robust hybrid algorithm named DEOSA for function optimization problems is investigated in this paper. In recent years, differential evolution (DE) has attracted wide research and effective applications in various fields. However, to the best of our knowledge, most of the available works did not consider noisy and uncertain environments in practical optimization problems. This paper focuses on a robust DE, which can adapt to noisy environment in real applications. By combining the advantages of DE algorithm, the optimal computing budget allocation (OCBA) technique and simulated annealing (SA) algorithm, a robust hybrid DE approach DEOSA is proposed. In DEOSA, the population-based search mechanism of DE is applied for well exploration and exploitation, and the OCBA technique is used to allocate limited sampling budgets to provide reliable evaluation and identification for good individuals. Meanwhile, SA is also applied in the hybrid approach to maintain the diversity of the population, in order to alleviate the negative influences on greedy selection mechanism of DE brought by the noises. DEOSA is tested by well-known benchmark problems with noise and the effect of noise magnitude is also investigated. The comparisons to several commonly used techniques for optimization in noisy environment are also carried out. The results and comparisons demonstrate the superiority of DEOSA.

In this paper, a memetic co-evolutionary differential evolution algorithm (MCODE) for constrained optimization is proposed. Two cooperative populations are constructed and evolved by independent differential evolution (DE) algorithm. The purpose of the first population is to minimize the objective function regardless of constraints, and that of the second population is to minimize the violation of constraints regardless of the objective function. Interaction and migration happens between the two populations when separate evolutions go on for several iterations, by migrating feasible solutions into the first group, and infeasible ones into the second group. Then, a Gaussian mutation is applied to the individuals when the best solution keep unchanged for several generations. The algorithm is tested by five famous benchmark problems, and is compared with methods based on penalty functions, co-evolutionary genetic algorithm (COGA), and co-evolutionary differential evolution algorithm (CODE). The results proved the proposed cooperative MCODE is very effective and efficient.