Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU) --- deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -- 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -- 80X higher. Moreover, using the CPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

Cell-based input-queued crossbars are widely used in networking equipments. A number of crossbar scheduling algorithms have been proposed to provide high performance scheduling. It is critical for a crossbar scheduling algorithm to be fair and efficient in real world conditions, which include the presence of over-subscribed ingress ports and the possible flow control from the egress ports. Several commonly deployed algorithms are not fair when there are ingress congestions due to over-subscription. Furthermore, these algorithms lose fairness and can even cause starvation when there is flow control or backpressure from the egress ports. We illustrate the problems in detail using the well-known iSLIP algorithm. In this paper, we present a new algorithm, iSKIP, which performs as efficiently as iSLIP in a benign environment but remains fair and starvation-free in the cases of ingress congestion and egress backpressure. The iSKIP algorithm can be implemented in fast and simple hardware. Simulation results are presented to illustrate the advantages of the iSKIP algorithm.

Distributed switch architectures allow the partition of a switch fabric into smaller independent switches, which is a key advantage for building high capacity switching systems, such as terabit switches. The performance and the feasibility of a distributed switch architecture depend on two critical components: the design of the queueing structure and the load balancing algorithm. In this paper, we present a distributed switch architecture with a simple yet efficient queueing structure and load-balancing algorithm that can be easily implemented in a terabit switch fabric with OC-768 line rate. The queueing structure is based on distributed non-buffered input-queued crossbar switch elements with request-only virtual output queues. The distributed load-balancing algorithm dynamically balances workloads among the parallel switch elements by trying to equalize the length of request-only virtual output queues in each of the switch elements. We refer to our architecture as a distributed switch architecture (ADSA), which introduces little communication overhead and no throughput degradation. As a result, it enables non-blocking switching without the need for internal speed-up. The load-balancing algorithm can perform one load-balancing action in less than 10 ns, which is suitable for OC-768 line rates of 40 Gbps. We study the performance of the ADSA architecture by modeling it as discrete-time queues with uniform i.i.d. Bernoulli traffic. We use a combination of analytical and simulation approaches to show that the ADSA can be approximated as discrete-time Geom/G/P queues under both light and heavy loads. Then the Allen-Cunneen approximation formula is applied to derive the mean cell delay of the ADSA architecture as a function of the underlying crossbar scheduling algorithm, the number of parallel switch elements and the number of ports in the system.