As scaling is more and more aggressive, intermittent faults are increasing their importance in current deep submicron complementary metal-oxide-semiconductor (CMOS) technologies. This work shows the dependability assessment of a fault-tolerant computer system against intermittent faults. The applied methodology lies in VHDL-based fault injection, which allows the assessment in early design phases, together with a high level of observability and controllability. The evaluated system is a duplex microcontroller system with cold stand-by sparing. A wide set of intermittent fault models have been injected, and from the simulation traces, coverages and latencies have been measured. Markov models for this system have been generated and some dependability functions, such as reliability and safety, have been calculated. From these results, some enhancements of detection and recovery mechanisms have been suggested. The methodology presented is general to any fault-tolerant computer system.

With the scaling of complementary metal-oxide-semiconductor (CMOS) technology to the submicron range, designers have to deal with a growing number and variety of fault types. In this way, intermittent faults are gaining importance in modern very large scale integration (VLSI) circuits. The presence of these faults is increasing due to the complexity of manufacturing processes (which produce residues and parameter variations), together with special aging mechanisms. This work presents a case study of the impact of intermittent faults on the behavior of a reduced instruction set computing (RISC) microprocessor. We have carried out an exhaustive reliability assessment by using very-high-speed-integrated-circuit hardware description language (VHDL)-based fault injection. In this way, we have been able to modify different intermittent fault parameters, to select various targets, and even, to compare the impact of intermittent faults with those induced by transient and permanent faults.

As technologies shrink, new kinds of faults arise. Intermittent faults are part of these new faults. They are expected to be an increasing challenge in modern VLSI circuits. Up to now, transient and permanent faults used to be injected for the experimental validation of fault tolerance mechanisms. The main objective of this work is to improve the dependability assessment by injecting also intermittent faults. Furthermore, we have compared intermittent faults impact with the influence of transient and permanent faults. To carry out this study, we have injected bursts of intermittent faults in a fault-tolerant microcomputer system with some well known fault detection and recovery mechanisms. The methodology used lies in VHDL-Based Fault Injection technique, which allows a systematic and exhaustive analysis. Results show that intermittent faults have a notable impact on recovery mechanisms. They must be taken into account besides permanent and transient faults to implement an accurate dependability assessment.

Intermittent faults are expected to be a great challenge in VLSI circuits. The complexity of manufacturing processes, provoking residues and process variations, and special wear out mechanisms, may increase the presence of such faults. This work presents a case study of the effects of intermittent faults on the behavior of a commercial micro controller. By using VHDL-based fault injection, particularly saboteurs, we have injected different intermittent fault models in the micro controller buses, as they are critical locations, potentially sensitive to intermittent faults. We have compared the impact and the feasibility of implementation of the fault models, in order to select a representative and low cost intermittent fault load. The applied methodology can be generalized to inject intermittent faults in other locations, such as registers and memory, and to validate the dependability of critical systems.

Deep submicrometer devices are expected to be increasingly sensitive to physical faults. For this reason, fault-tolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior concern in the design process. Fault injection techniques based on the use of hardware description languages offer important advantages with regard to other techniques. First, as this type of techniques can be applied during the design phase of the system, they permit reducing the time-to-market. Second, they present high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high fault modeling capability. However, implementing automatically these techniques in a fault injection tool is difficult. Especially complex are the insertion of saboteurs and the generation of mutants. In this paper, we present new proposals to implement saboteurs and mutants for models in VHDL which are easy-to-automate, and whose philosophy can be generalized to other hardware description languages.

During last years, the time-triggered architecture (TTA) has been gaining acceptance as a generic architecture for highly dependable real-time systems. It is now being used to implement the "x-by-wire " concept. A problem for this kind of systems is their validation. Fault injection has achieved a great acceptance among designers for the experimental validation of systems. This work describes the results and experiences obtained during the validation of the TTP/C controller, a communication controller based on the TTA. Two different fault-injection techniques have been used: VHDL-based fault injection and physical fault injection at pin level. Due to the access that each technique has to different parts of the system, they can complement each other, but moreover, some experiments can be reproduced using both techniques, being very helpful for the analysis of the results.

As the use of dependable systems is generalising, their study in early phases of the design cycle is more and more important in order to save time and money. In this work, using a generic VEDL-based fault injection tool, called VFIT (VHDL-Based Fault Injection Tool), we have validated the dependability of a real Fault-Tolerant System using its VHDL model. The system studied is based on the Time-Triggered Architecture. It is a synchronous protocol with static scheduling that has been specifically targeted at hard real-time fault-tolerant distributed system. The use of this system is growing in aircraft and automotive areas (x-by-wire). We have analysed the pathology of the propagated errors, measured their latencies, and calculated both error detection latencies and coverages. As the main conclusion of this work, we have detected an erroneous implementation of the firmware of the controller as well as results show that built-in selftest mechanisms detect the larger part of errors.