In the fast-growing electric vehicle (EV) industry, key technology challenges include the improvement of battery efficiency, reliability, and endurance. In this paper, we propose a novel battery pack design methodology that supports dynamic reconfiguration of the battery pack architecture, which partitions the battery modules into the primary group and secondary group. The proposed reconfigurable design effectively improves the battery pack reliability and endurance, especially for battery packs that contain modules with uneven aging conditions. Simulation results show that, with our approach, the equivalent average aging speed among all battery modules is slowed down, and the battery pack's endurance is increased.

The global warming and pollution issues have reached an alarming level that requires immediate actions by all governments in the world to reduce fossil fuel vehicles, and even ban them in the foreseeable future. As a result, electric vehicles (EVs) are gaining ground rapidly. Inside the EVs, especially their power train, semiconductor power devices are considered the key components. Increasing the performance, energy efficiency, and reliability of power MOSFET, therefore, is critical in the EV industry. In this work, we stress the reliability and lifetime of power MOSFET devices and propose an aging model for them. We will show the procedure to construct the efficient aging model for a power MOSFET, supported by circuit-level simulation results. The aging conditions, including high temperature and/or high voltage on the gate oxide, will result in threshold voltage shift, which in turn decreases the MOSFET's switching speed and driving capability. With the proposed aging assessment tool for power MOSFET, the device's performance under different aging conditions can be predicted. The experiment results show that aging will reduces its switching speed and driving power. Experimental results by our tool also show that the circuit efficiency, ripple voltage, switching loss, etc., are negatively affected by aging.

Three-dimensional dynamic random access memory (3D DRAM) using through-silicon via (TSV) has been acknowledged as one good approach for overcoming the memory wall. However, the IO-channel power of a TSV-based 3D DRAM represents a significant portion of the 3D DRAM power. In this paper, we propose a built-in self-test (BIST) -assisted tuning scheme to adjust the driving capability of programmable drivers to fit the number of stacked 3D DRAM dies such that the IO-channel power can be minimized. A BIST design supporting specific test patterns and test flow for the driver tuning is proposed as well. Simulation results show that about 6.16×10 -- 2 J energy saving can be achieved for a logic-DRAM stack with 150fF/die TSV load under 100s write operations if the proposed BIST-assisted tuning scheme is implemented in the logic die.

Error control codes (ECCs) have been widely used to maintain the reliability of memories, but ordinary ECC codes are not suitable for memories with long codewords. For portable products, power reduction in memories with DRAM-like cells can be done by reducing the refresh frequency, but the loss of data integrity should be taken care of seriously. To solve these issues, we have proposed a parallel encoding and decoding ECC scheme to reduce refresh power for an industrial pseudo-SRAM (PSRAM) with long codewords. In this paper, we briefly review the scheme and propose a systematic way to generate the parity check matrix for the new ECC scheme. We also modify the parity correction mechanism to reduce the operating power of the scheme. As for the 70 ns access time of the 256-MB PSRAM with 64-bit codewords and 16-bit I/O, experimental results show that the new ECC scheme can be integrated with the READ/WRITE operations with about 0.2 percent circuit area overhead and less than 3.5 ns encoding/decoding time. The new ECC architecture provides a flexible solution for memories with different widths of ECC codewords and I/O ports, without the error masking effect or reduction in reliability.

The advancement of deep submicrometer Integrated circuit manufacturing technology has pushed the use of embedded memory, and the strong demand of embedded nonvolatile memory for system-on-chip and system in package applications has made flash memory increasingly important as well. Nevertheless, the yield loss of memory products caused by deep submicrometer defects and manufacturing uncertainties is still a critical issue. In order to solve the yield issue, built-in self-repair (BISR) has been considered as the most cost-effective solution. However, implementing BISR on flash memories is not trivial. In this paper, we propose BISR schemes for nor flash memory and NAND flash memory, respectively. The BISR schemes perform built-in self-test, built-in redundancy analysis, and on-chip repair. For the BISR scheme of nor flash memory, a typical redundancy architecture is assumed, based on which we analyze three existing algorithms and propose a redundancy analysis (RA) algorithm. On the other hand, for NAND flash memory, an RA algorithm based on an efficient 2-D redundancy architecture is proposed, and considering the widely used page-mode operation in NAND flash memory, a method to discover currently accessed address is also proposed. A simulation tool is also developed, supporting nor flash memory and NAND flash memory. The simulation results show that our approach can effectively repair defective memories.

As feature size keeps shrinking, how to maintain the reliability becomes an important issue in IC production, especially for high density memory circuits. Error detection and correction (EDAC) schemes have been widely used for memory circuits for this purpose, but ordinary EDAC schemes are not suitable for memories with long codewords. The demand for low-power memory is increasing due to the growth in portable electronics markets. Power reduction in memories with DRAM-like cells can be done by reducing the refresh frequency, but the loss of data integrity should be taken care of seriously. To solve the above two issues, we propose a parallel encoding and decoding EDAC scheme, which can be used on memories with long codewords. Targeting refresh power reduction, we have implemented our scheme on an industrial pseudo SRAM (PSRAM), and have completed experiments. The major hardware penalty is the parity overhead that is 1/9, and the longest delay of our circuit is 3.6ns for the PSRAM fabricated by a 0.11mum CMOS technology. With respect to the 70ns access time of the PSRAM, the proposed EDAC scheme can be integrated with the read/write operations without increasing the latency. Experimental results show that the refresh time can be extended greatly, without sacrificing reliability

The strong demand of non-volatile memory for SOC and SIP applications has made flash memory increasingly important. However, deep submicron defects and process uncertainties are causing yield loss of memory products. To solve the yield issue, built-in self-repair (BISR) is widely believed to be cost effective. It is, however, non-trivial to implement BISR on flash memories. In this paper we propose a BISR scheme for NOR-type flash memory. The BISR scheme performs built-in self-test (BIST), built-in redundancy analysis (BIRA), as well as on-chip repair. A typical redundancy architecture for NOR-type flash memory is assumed, based on which we present a redundancy analysis (RA) algorithm. Experimental result shows that the proposed BISR scheme can effectively repair most defective memories.

As the memory cells keep scaling down and designs are getting bigger and faster, uncertainty is becoming one of the greatest challenges for the semiconductor industry. Unexpected and unpredictable behaviors of devices usually lead to poor quality and reliability. Low-cost test techniques that improves die sorting accuracy thus are critical for advanced devices. Flash memory is more prone to such problem compared with others. Large capacity, high density, and complicated cell structure makes flash memory cell behavior difficult to predict precisely. Even when we test the dies on the same wafer it can be bothering, as each of them may ask for different test condition due to geometric process variation. As a fast and easy-to-use method to solve the problem, we propose a sample classification method. It is not only effective for flash memory testing, but also for other types of circuits that face similar test problem. Experimental result shows that the method solves the flash memory die sort problem efficiently and accurately. The test time is greatly reduced-for an industrial chip, the test time is reduced from 8,817 ms to 718 ms. Moreover, the proposed approach is also suitable for design-for-testability (DFT) implementation that can easily be integrated with a commodity or embedded memory.