Article Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor Share on Authors: Norman Kojima Design Methodology Dept., System LSI Design Div., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan Design Methodology Dept., System LSI Design Div., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, JapanView Profile , Yukiko Parameswar Toshiba America Elec. Components, Inc., 1060 Rincon Circle, San Jose, California Toshiba America Elec. Components, Inc., 1060 Rincon Circle, San Jose, CaliforniaView Profile , Christian Klingner Toshiba America Elec. Components, Inc., 1060 Rincon Circle, San Jose, California Toshiba America Elec. Components, Inc., 1060 Rincon Circle, San Jose, CaliforniaView Profile , Yukio Ohtaguro System ULSI Engineering Lab., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, JapanView Profile , Masataka Matsui System ULSI Engineering Lab., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, JapanView Profile , Shigeaki Iwasa RISC Processor Development Dept., Microprocessor Div., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan RISC Processor Development Dept., Microprocessor Div., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, JapanView Profile , Tatsuo Teruyama Microprocessor Design Dept., System LSI Design Div., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan Microprocessor Design Dept., System LSI Design Div., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, JapanView Profile , Takayoshi Shimazawa System ULSI Engineering Lab., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, JapanView Profile , Hideki Takeda System ULSI Engineering Lab., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, JapanView Profile , Kouji Hashizume Advanced LSI Technology Development Dept., Toshiba Microelectronics Corp., 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan Advanced LSI Technology Development Dept., Toshiba Microelectronics Corp., 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, JapanView Profile , Haruyuki Tago System ULSI Engineering Lab., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan System ULSI Engineering Lab., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, JapanView Profile , Masaaki Yamada Design Methodology Dept., System LSI Design Div., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan Design Methodology Dept., System LSI Design Div., Toshiba Corporation Semiconductor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, JapanView Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 641–646https://doi.org/10.1145/368434.368852Online:28 January 2000Publication History 5citation138DownloadsMetricsTotal Citations5Total Downloads138Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Electromagnetic compatibility (EMC) has become more and more important in designing electronic systems. Although electromagnetic radiation itself mainly occurs from off-chip conductors, the ultimate noise source is in LSI chips. Among the noise distribution paths, the power-line conducting noise is the most significant source of electromagnetic interference (EMI)-noise caused by LSIs. This paper introduces an EMI-noise analysis method suitable for application-specific integrated circuit design environment especially focusing on the power-line conducting noise. Modeling method for power network and switching activity, simulation flow, and experimental results are presented. Experimental results show that our modeling methodology estimates capacitance values with sufficient accuracy and reproduces the relative differences in EMI-noise levels.

Electromagnetic compatibility (EMC) has become more and more important in designing electronic systems. Although electromagnetic radiation itself mainly occurs from off-chip conductors, the ultimate noise source is in LSI chips. Among the noise distribution paths, the power-line conducting noise is the most significant source of electromagnetic interference (EMI)-noise caused by LSIs. This paper introduces an EMI-noise analysis method suitable for application-specific integrated circuit design environment especially focusing on the power-line con- ducting noise. Modeling method for power network and switching activity, simulation flow, and experimental results are presented. Experimental results show that our modeling methodology esti- mates capacitance values with sufficient accuracy and reproduces the relative differences in EMI-noise levels. Index Terms—ASIC, EMI-noise, LSI, simulation.

A floorplanner, FOLM-planner, suitable for SOG gate arrays is presented. FOLM-planner is based on a 'frame overlapping floorplan model, which is free from unnecessary constraints caused by conventional floorplan models, and is easy to use for satisfying timing constraints. FOLM-planner aims at minimizing the net length among frames and controlling frame overlaps for efficient usage of a chip area. To accomplish these objectives, FOLM-planner uses a newly developed force directed method for frame reshaping as well as moving. Experimental results have shown that FOLM layout can shorten the net length inside a frame without the total net length becoming longer.>

A study, motivated by the goal of integrating the placement and routing steps in the physical design of VLSI circuits, of the pin assignment problem for macrocells is discussed. It is assumed that the macrocells have already been placed. It is also assumed that the design of the macrocells is still soft in that although the pins in a cell have a fixed relative order, they can be shifted around the boundary of the cell. An algorithm to determine how the pins are to be shifted so that the weighted sum of the lengths of the connecting wires is minimal is developed. Good experimental results were obtained.>