Abstract Programmable logic controllers (PLCs) are widely used in industrial applications. Ensuring the correctness of PLC programs is important due to their safety-critical nature. Structured text (ST) is an imperative programming language for PLC. Despite recent advances in executable semantics of PLC ST, existing methods neglect complex multitasking and preemption features. This paper presents an executable semantics of PLC ST with preemptive multitasking. Formal analysis of multitasking programs experiences the state explosion problem. To mitigate this problem, this paper also proposes state space reduction techniques for model checking multitask PLC ST programs.

This paper presents a feasible study of fully-integrated switching voltage regulators for power-optimized systems-on-chip (SoCs). In order to evaluate the power efficiency across a number of design variables, a compact macro-model of a regulator is created and validated. A key focus of the study is on the characteristics of the active and passive devices that are needed in order to maximize the efficiency of an on-chip regulator. With the macro-model, geometric programming is used to find the optimal characteristics for a given set of constraints such as load condition, process technology, and area. The achievable efficiencies for various current loads and across a range of technologies from 0.35-mum to 90-nm CMOS process are analyzed. The power efficiency is found to be strongly dependent on the inductor technology and over 70% efficiency is possible with advanced inductor technologies.

We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the results from optimization and simulation, and propose several methods to reduce the error. Device modeling based on convex piecewise-linear (PWL) function fitting is introduced to create accurate active and passive device models. We also show that in selected cases GP can enable nonconvex constraints such as bias constraints using monotonicity, which help reduce the error. Lastly, we suggest a simple method to take the modeling error into account in GP optimization, which results in a robust design over the inherent errors in GP device models. Two-stage operational amplifier and on-chip spiral inductor designs are given as examples to demonstrate the presented ideas.