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Carl L. Gardner

dblp:58/6115 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 1991
0000-0001-8967-3356ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 61% Integrated circuit design · 26% High-performance computing · 13%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Computational science and engineering · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › technology computer-aided design
device simulation
0.021991
A parallel block iterative method for the hydrodynamic device model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Numerical methods for the hydrodynamic device model: subsonic flow · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Integrated circuit design › semiconductor device modeling
hydrodynamic device model
0.021991
A parallel block iterative method for the hydrodynamic device model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Numerical methods for the hydrodynamic device model: subsonic flow · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation › technology computer-aided design › process simulation
dopant diffusion modeling
0.011991
Two-dimensional process simulation using verified phenomenological models · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
High-performance computing
parallel numerical algorithms
0.011991
A parallel block iterative method for the hydrodynamic device model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › technology computer-aided design
process simulation
0.011991
Two-dimensional process simulation using verified phenomenological models · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › technology computer-aided design › process simulation
two-dimensional process simulation
0.011991
Two-dimensional process simulation using verified phenomenological models · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Computational science and engineering
numerical analysis
0.011989
Numerical methods for the hydrodynamic device model: subsonic flow · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Integrated circuit design
semiconductor device modeling
0.011991
Two-dimensional process simulation using verified phenomenological models · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991

Methods — techniques the papers use, named apart from their topics

nonlinear wave analysis · 0.0hydrodynamic model · 0.0block iterative method · 0.0preconditioned conjugate gradient · 0.0phenomenological diffusion models · 0.0numerical simulation · 0.0chaotic relaxation · 0.0block successive underrelaxation · 0.0
YearPublicationVenuePosition
1991 Two-dimensional process simulation using verified phenomenological models
abstract
Two-dimensional (2-D) effects are becoming increasingly important in the diffusion of impurities in submicrometer silicon devices. The authors describe a 2-D process simulator, PREDICT2, that handles implant damage effects, annealing, and lateral diffusion. PREDICT2 simulates the diffusion of impurities in silicon by using phenomenological diffusion coefficients. The phenomenological models are verified by comparing simulated and experimental results. This approach is compared with that of point-defect-based simulators. The experimental technique for measuring impurity profiles in two dimensions is outlined. The method for generating diffusion models is illustrated by examining 2-D phosphorous diffusion. Numerical simulations and experimental measurements are compared. The numerical methods used in the simulator are described, and directions for future work are suggested.>
Richard B. Fair, Carl L. Gardner, Michael J. Johnson, Stephen W. Kenkel, Donald J. Rose, John E. Rose, Ravi Subrahmanyan
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1991 A parallel block iterative method for the hydrodynamic device model
abstract
Block iterative methods are applied to hydrodynamic simulations of a one-dimensional submicrometer semiconductor device. It is shown that block successive underrelaxation (SUR) converges with a fixed relaxation factor omega =0.13 for simulations at 300 K and omega =0.04 at 77 K. To demonstrate the robustness of the block iterative method, numerical simulations of a steady-state electron shock wave in Si at 300 K for a 0.1- mu m channel and at 77 K for a 1.0- mu m channel are presented. The block SUR method is parallelizable if each diagonal block solve can be done efficiently in parallel. Using chaotic relaxation and the preconditioned conjugate gradient method for the parallel diagonal block solves, a parallel speed up of approximately 2.5 is obtained on 10 processors of a Butterfly GP-1000.>
Carl L. Gardner, Paul J. Lanzkron, Donald J. Rose
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1989 Numerical methods for the hydrodynamic device model: subsonic flow
abstract
An introduction to the hydrodynamic model for semiconductor devices is presented. Special attention is paid to classifying the hydrodynamic PDEs (partial differential equations) and analyzing their nonlinear wave structure. Numerical simulations of the ballistic diode using the hydrodynamical device model are presented, as an illustrative elliptic problem. The importance of nonlinear block iterative methods is emphasized. Arguments for existence of solutions and convergence of numerical methods are given for the case of subsonic electron flow.>
Carl L. Gardner, Joseph W. Jerome, Donald J. Rose
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1