Timing-driven placement is very important to achieve timing closure especially as designs become increasingly complex. This article presents a novel Timing-Driven Placement (TDP) framework that integrates a graph convolutional network (GCN), Dirichlet boundary conditions, and a nonlinear placement engine to optimize placement quality with timing awareness throughout the flow. The proposed methodology begins by clustering components based on their interconnection topology, while Dirichlet boundary conditions are applied to handle fixed components such as IOs and macros. This yields a reduced graph with minimized inter-cluster connectivity, simplifying timing optimization. A GCN is then trained to learn a generalized and optimized mapping from circuit connectivity to physical wirelength. To improve early-stage timing estimation, virtual buffers are inserted prior to Static Timing Analysis (STA) to eliminate maximum capacitance violations. With this improved timing fidelity, STA provides pin-level slack, which is then used to dynamically adjust interconnection weights, guiding the placement of timing-critical components toward improved timing closure. Experimental results on ICCAD2015 contest benchmarks demonstrate that our algorithm can improve worse negative slack and total negative slack by 6% compared to the state-of-the-art method.

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This article proposes GiFt, a parameter-free initialization technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multiresolution smooth signals of circuit graphs to generate optimized initial placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Moreover, we present GiFtPlus, an enhanced version of GiFt, which is more efficient in handling large-scale circuit placement and can accommodate location constraints. Experimental results on public benchmarks show that GiFt and GiFtPlus significantly improve placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, the recently proposed GPU-accelerated analytical placer DREAMPlace uses up to 50% more total runtime than GiFtPlus-DREAMPlace.

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics.

Floorplanning is a complex physical design problem that produces initial locations of movable objects, the quality of which has a great impact on downstream tasks such as placement and routing. To improve the efficacy of floorplanning, machine learning techniques have recently been recruited for help. However, the application-specific location constraints (IOs and cells with fixed locations) pose a huge challenge for machine learning. This article presents a novel uniformization approach by Dirichlet boundary conditions, which decomposes floorplanning into two easier-to-solve subproblems, namely a convex quadratic wirelength optimization problem with location constraints and an NP-hard combinatorial problem with homogeneous Dirichlet boundary conditions. The former problem is efficiently solved using quadratic optimization, and the latter is addressed by efficient graph inference using the proposed hierarchical GNN-based model. The proposed floorplanner called DPlanner has been integrated with state-of-the-art mixed-size placers to generate high-quality placement solutions with up to 56% and 41% improvement in placement iterations and runtime. In addition, compared to the state-of-the-art integrated floorplanning-placement flow, DPlanner achieves over a 20% improvement in placement iteration and more than a 21% reduction in total runtime, along with a 2% average reduction in wirelength.

Chip floorplanning has long been a critical task with high computation complexity in the physical implementation of VLSI chips. Its key objective is to determine the initial locations of large chip modules with minimized wirelength while adhering to the density constraint, which in essence is a process of constructing an optimized mapping from circuit connectivity to physical locations. Proven to be an NP-hard problem, chip floorplanning is difficult to be solved efficiently using algorithmic approaches. This article presents GraphPlanner, a variational graph-convolutional-network-based deep learning technique for chip floorplanning. GraphPlanner is able to learn an optimized and generalized mapping between circuit connectivity and physical wirelength and produce a chip floorplan using efficient model inference. GraphPlanner is further equipped with an efficient clustering method, a unification of hyperedge coarsening with graph spectral clustering, to partition a large-scale netlist into high-quality clusters with minimized inter-cluster weighted connectivity. GraphPlanner has been integrated with two state-of-the-art mixed-size placers. Experimental studies using both academic benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers alone, GraphPlanner improves placement runtime by 25% with 4% wirelength reduction on average.

Floorplanning has long been a critical physical design task with high computation complexity. Its key objective is to determine the initial locations of macros and standard cells with optimized wirelength for a given area constraint. This paper presents Flora, a graph attention-based floorplanner to learn an optimized mapping between circuit connectivity and physical wirelength, and produce a chip floorplan using efficient model inference. Flora has been integrated with two state-of-the-art mixed-size placers. Experimental studies using both academic benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers alone, Flora improves placement runtime by 18%, with 2% wirelength reduction on average.

Energy consumption and the associated environmental impact are a pressing challenge faced by the transportation sector. Emerging electric-drive vehicles have shown promises for substantial reductions in petroleum use and vehicle emissions. Their success, however, has been hindered by the limitations of energy storage technologies. Existing in-vehicle lithium-ion battery systems are bulky, expensive, and unreliable. Energy storage system (ESS) design and optimization is essential for emerging transportation electrification. This paper presents an integrated ESS modeling, design, and optimization framework targeting emerging electric-drive vehicles. A large-scale ESS modeling solution is first presented, which considers major runtime and long-term battery effects, and uses fast frequency-domain analysis techniques for efficient and accurate characterization of large-scale ESS. The proposed design framework unifies design-time optimization and runtime control. This conducts statistical optimization for ESS cost and lifetime, which jointly considers the variances of ESS due to manufacture tolerance and heterogeneous driver-specific runtime usage. This optimizes ESS design by incorporating complementary energy storage technologies, e.g., lithium-ion batteries and ultracapacitors. Using physical measurements of battery manufacture variation and real-world user driving profiles, our experimental study has demonstrated that the proposed framework effectively explores the statistical design space and produces cost-efficient ESS solutions with statistical system lifetime guarantees.

Retiming is one of the most powerful sequential transformations that relocates flip-flops in a circuit without changing its functionality. The min-period retiming problem seeks a solution with the minimal clock period. Since most min-period retiming algorithms assume a simple constant delay model that does not take into account many prominent electrical effects in ultra deep sub micron vlsi designs, a general delay model was proposed to improve the accuracy of the retiming optimization. Due to the complexity of the general delay model, the formulation of min-period retiming under such model is based on integer linear programming (ILP). However, because the previous ILP formulation was derived on a dense path graph, it incurred huge storage and running time overhead for the ILP solvers and the application was limited to small circuits. In this paper, we present the iRetILP algorithm to solve the min-period retiming problem efficiently under the general delay model by formulating and solving the ILP problems incrementally. Experimental results show that iRetILP is on average 100× faster than the previous algorithm for small circuits and is highly scalable to large circuits in term of memory consumption and running time.

Energy consumption and the associated environmental impact are a pressing challenge faced by the transportation sector. Emerging electric-drive vehicles have shown promises for substantial reductions in petroleum use and vehicle emissions. Their success, however, has been hindered by the limitations of energy storage technologies. Existing in-vehicle Lithium-ion battery systems are bulky, expensive, and unreliable. Energy storage system (ESS) design and optimization is essential for emerging transportation electrification. This paper presents an integrated ESS modeling, design and optimization framework targeting emerging electric-drive vehicles. Based on an ESS modeling solution that considers major run-time and long-term battery effects, the proposed framework unifies design-time optimization and run-time control. It conducts statistical optimization for ESS cost and lifetime, which jointly considers the variances of ESS due to manufacture tolerance and heterogeneous driver-specific run-time use. It optimizes ESS design by incorporating complementary energy storage technologies, e.g., Lithium-ion batteries and ultracapacitors. Using physical measurements of battery manufacture variation and real-world user driving profiles, our experimental study has demonstrated that the proposed framework can effectively explore the statistical design space, and produce cost-efficient ESS solutions with statistical system lifetime guarantee.

This paper describes a new floorplanning approach called constrained adjacency graph (CAG) that helps exploring adjacency in floorplans. CAG extends the previous adjacency graph approaches by adding explicit adjacency constraints to the graph edges. After sufficient and necessary conditions of CAG are developed based on dissected floorplans, CAG is extended to handle general floorplans in order to improve area without changing the adjacency relations dramatically. These characteristics are currently utilized in a randomized greedy improvement heuristic for wire length optimization. The results show that better floorplans are found with much less running time for problems with 100 to 300 modules in comparison to a simulated annealing floorplanner based on sequence pairs.

Advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variables. It remains a challenge problem to apply such results in order to address the variability in circuit optimizations. In this paper, we study the statistical retiming problem, where retiming is a powerful sequential transformation that relocates flip-flops in a circuit without changing its functionality. We formulate the risk aversion min-period retiming problem under process variations based on conventional two-stage stochastic program with fixed recourse and a risk aversion objective of the clock period. We prove that the proposed problem is an integer convex program, show that the subgradient of the objective function can be derived from the combinational paths with the maximum path delay, and present a heuristic incremental algorithm to solve the proposed problem. Our approach can handle arbitrary gate delay model under process variations through sampling from a black-box and the effectiveness is confirmed by the experimental results. Further more, we point out how the current state-of-the-art SSTA techniques could be improved for future optimization algorithms when analytical models are available.

In this paper, we formulate the generalized convex sizing (GCS) problem that unifies the sizing problems and applies to sequential circuits with clock-skew optimization. We revisit the approach to solve the sizing problem by Lagrangian relaxation, point out several misunderstandings in the previous paper, and extend the approach to handle general convex delay functions in the GCS problems. We identify a class of proper GCS problems whose objective functions in the simplified dual problem are differentiable and transform the simultaneous sizing and clock-skew optimization problem into a proper GCS problem. We design an algorithm based on the method of feasible directions and min-cost network flow to solve proper GCS problems. The algorithm will provide evidences for infeasible GCS problems according to a condition derived by us. Experimental results confirm the efficiency and the effectiveness of our algorithm when the Elmore delay model is used.

As one of the most effective sequential optimization techniques, retiming is a structural transformation that relocates flip-flops in a circuit without changing its functionality. The min-area retiming problem seeks a solution with the minimum flip-flop area (or number) under a given clock period. Even though having polynomial runtime, the best existing algorithms for this problem still need to first construct a dense path graph and then find a min-cost network flow on it, thus incur huge storage and time expenses for large circuits. Recently, provable incremental algorithms have been discovered for min-period retiming, and heuristic incremental algorithms have been proposed for min-area retiming. However, given the complexity of the problem, min-area retiming is still resisting an efficient provable incremental algorithm. In this paper, we fill the gap by presenting an efficient algorithm to solve the min-area retiming problem incrementally and optimally. Contrary to existing approaches, no dense path graph is constructed; only the active timing constraints are dynamically generated in the algorithm. Experimental results show that the total runtime of our algorithm for all the benchmarks is at least 60 x faster than the best existing approach.

In this paper, we propose the linear constraint graph (LCG) as an efficient general floorplan representation. For n blocks, an LCG has at most 2n+3 vertices and at most 6n+2 edges. Operations with direct geometric meanings are developed to perturb the LCGs. We apply the LCGs to the floorplan optimization with soft blocks to leverage its advantage in terms of the sizes of the graphs, which will improve the efficiency of solving a complex mathematical program in the inner loop of the optimization that decide the block shapes without introducing overlaps to the non-slicing floorplans. Experimental results confirm that the LCGs are effective and efficient.

Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with CMOS circuits, nanowire decoders were invented. Due to the stochastic nature of the nanoscale fabrication, the decoder addresses that address the nanowires selectively must be generated after fabrication. In this paper, we develop a mathematical model of the nanowire decoders for the generation of the proper addresses. Assuming a simple testing approach calledon-off measurement, we prove that the maximum number of the proper addresses can be generated in finite time. We design the algorithms to generate the required number of the proper addresses. Experimental results confirm the efficiency of our algorithms.

In this paper, we formulate the generalized convex sizing (GCS) problem that unifies and generalizes the sizing problems. We revisit the approach to solve the sizing problem by Lagrangian relaxation, point out several misunderstandings in the previous works, and extend the approach to handle general convex delay functions in the GCS problems. We identify a class of proper GCS problems whose objective functions in the simplified dual problem are differentiable and show many practical sizing problems, including the simultaneous sizing and clock skew optimization problem, are proper. We design an algorithm based on the method of feasible directions to solve proper GCS problems. The algorithm will provide evidences for infeasible GCS problems according to a condition derived by us. Experimental results confirm the efficiency and the effectiveness of our algorithm when the Elmore delay model is used.

Achieving design closure is one of the biggest challenges for modern very large-scale integration system designers. This problem is exacerbated by the lack of high-level design-automation tools that consider the increasingly important impact of physical features, such as interconnect, on integrated circuit area, performance, and power consumption. Using physical information to guide decisions in the behavioral-level stage of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level-synthesis system. This system integrates high-level and physical-design algorithms to concurrently improve a design's schedule, resource binding, and floorplan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefits of efficiency, stability, and better quality of results. The average CPU time speedup resulting from unifying incremental physical-level and high-level synthesis is 24.72times and area improvement is 13.76%. The low power consumption of a state-of-the-art low-power interconnect-aware high-level-synthesis algorithm is maintained. The benefits of concurrent behavioral-level and physical-design optimization increased for larger problem instances.

Antenna effect may damage gate oxides during a plasma-based fabrication process. The antenna ratio of total exposed antenna area to total gate oxide area is directly related to the amount of damage. Jumper insertion is a common technique applied at routing and post-layout stages to avoid and to fix the problems caused by the antenna effect. This paper presents an optimal algorithm for jumper insertion under the ratio upper bound. It handles Steinbok trees with obstacles. The algorithm is based on dynamic programming while working on free trees. The time complexity is and the space complexity is , O (alpha|V|2) and the space complexity is (alpha|V|2) where |V| is the number of nodes in the routing tree and is alpha factor depending on how to find a nonblocked position on a wire for a jumper.

Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performance. It is necessary to consider thermal effects during all levels of the design process, from the architectural level to the physical level. However, design-time temperature prediction requires access to block placement, wire models, power profile, and a chip-package thermal model. Thermal-aware design and synthesis necessarily couple architectural-level design decisions (e.g., scheduling) with physical design (e.g., floorplanning) and modeling (e.g., wire and thermal modeling). This article proposes an efficient and accurate thermal-aware floor-planning high-level synthesis system that makes use of integrated high-level and physical-level thermal optimization techniques. Voltage islands are automatically generated via novel slack distribution and voltage partitioning algorithms in order to reduce the design's power consumption and peak temperature. A new thermal-aware floorplanning technique is proposed to balance chip thermal profile, thereby further reducing peak temperature. The proposed system was used to synthesize a number of benchmarks, yielding numerous designs that trade off peak temperature, integrated circuit area, and power consumption. The proposed techniques reduces peak temperature by 12.5degC on average. When used to minimize peak temperature with a fixed area, peak temperature reductions are common. Under a constraint on peak temperature, integrated circuit area is reduced by 9.9% on average

Antenna effect may damage gate oxides during plasma-based fabrication process. The antenna ratio of total exposed antenna area to total gate oxide area is directly related to the amount of damage. Jumper insertion is a common technique applied at routing and post-layout stages to avoid and to fix the problems caused by the antenna effect. This paper presents an optimal algorithm for jumper insertion under the ratio upper-bound. It handles Steiner trees with obstacles. The algorithm us based on dynamic programming while works on free trees. The time complexity is O(/spl alpha/|V|/sup 2/ ) and the space complexity is O(|V|/sup 2/), where |V| is the number of nodes in the routing tree and a is a factor depending on how to find a non-blocked position on a wire for a jumper.

Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level may have timing closure problems at post-layout stages due to the emergence of multiple-clock-period interconnects. Consequently, a tradeoff between clock frequency and throughput may be needed to meet the design requirements. In this paper, we find that the processing rate, defined as the product of frequency and throughput, of a sequential system is upper bounded by the reciprocal of its maximum cycle ratio, which is only dependent on the clustering. We formulate the problem of processing rate optimization as seeking an optimal clustering with the minimal maximum-cycle-ratio in a general graph, and present an iterative algorithm to solve it. Experimental results validate the efficiency of our algorithm

ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a representation sharing the advantage of adjacency graphs. As most edges in an ACG are between modules that are close to each other, the physical distance of two modules can be measured without packing by the shortest path between them on the ACG. Experimental results verified this relationship and possible approaches for interconnect planning are discussed.

Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly important factors such as the impact of interconnect on the area and power consumption of integrated circuits. Bringing physical information up into the logic level or even behavioral-level stages of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level synthesis system. This system integrates high-level and physical design algorithms to concurrently improve a system's schedule, resource binding, and floorplan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefit of effi- ciency, stability, and better quality of results. For designs containing functional units with non-unity aspect ratios, the average CPU time improved by 369 %, the area improved by 14.24%, and power improved by 4%.

Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level may have timing closure problems at post-layout stages due to the emergence of multiple-clock-period interconnects. Consequently, a trade-off between clock frequency and throughput may be needed to meet the design requirements. In this paper, we find that the processing rate, defined as the product of frequency and throughput, of a sequential system is upper bounded by the reciprocal of its maximum cycle ratio, which is only dependent on the clustering. We formulate the problem of processing rate optimization as seeking an optimal clustering with the minimal maximum-cycle-ratio in a general graph, and present an iterative algorithm to solve it. Since our algorithm avoids binary search and is essentially incremental, it has the potential of being combined with other optimization techniques. Experimental results validate the efficiency of our algorithm.

With aggressive scaling down of feature sizes in VLSI fabrication, process variations have become a critical issue in designs. With process variations, timing optimization should consider the randomness introduced in delays. This paper considers how to retime a circuit under process variations. A statistical retiming problem is defined on the concept of a disutility function. Based on a new minimal period retiming algorithm, two algorithms are presented for the statistical retiming problem. Both theoretical and experimental results are given.

ACG (adjacent constraint graph) is invented as a general floorplan representation. It has advantages of both adjacency graph and constraint graph of a floorplan: edges in an ACG are between modules close to each other, thus the physical distance of two modules can be measured directly in the graph; since an ACG is a constraint graph, the floorplan area and module positions can be simply found by longest path computations. A natural combination of horizontal and vertical relations within one graph renders a beautiful data structure with full symmetry. The direct correspondence between geometrical positions of modules and ACG structures also makes it easy to incrementally change a floorplan and evaluate the result. Experimental results show the superiority of this representation.